ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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Table 25. Link Ports—Receive
Parameter
Timing Requirements
t1
LXCLK_RX
Receive Link Clock Period
t2
LXCLKH_RX
t3
LXCLKH_RX
t2
LXCLKL_RX
t3
LXCLKL_RX
tDIS
tDIH
Receive Link Clock Width High
Receive Link Clock Width High
Receive Link Clock Width Low
Receive Link Clock Width Low
LxDAT7–0 Input Setup
LxDAT7–0 Input Hold
Min
0.9 × LR × 4 ns or
0.9 × LR + tCCLK,
whichever is larger
0.33 × tLXCLK_RX
0.4 × tLXCLK_RX
0.33 × tLXCLK_RX
0.4 × tLXCLK_RX
0.6
0.6
Switching Characteristics
tCONNV
Connectivity Pulse Valid
tCONNOW
Connectivity Pulse Output Width
0
1.5 × tLXCLK_RX
1 The link clock ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
2 The formula for this parameter applies when LR is 2.
3 The formula for this parameter applies when LR is 3, 4, or 8.
ADSP-TS101S
Max
1.1 × LR × tCCLK
0.66 × tLXCLK_RX
0.6 × tLXCLK_RX
0.66 × tLXCLK_RX
0.6 × tLXCLK_RX
2.5 × tLXCLK_RX
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
LxCLKIN
LxCLKOUT
tCONNV
1
0
tLxCLK_Rx
tLxCLKH_Rx
tDIH
tDIH
tLxCLKL_Rx tDIS
tDIS
3
5
7
9
11
13
15
2
4
6
8
10
12
14
tCONNOW
LxDAT7–0
LxDIR
Figure 11. Link Ports—Receive
REV. A
–29–
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