ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
Table 23. AC Signal Specifications (for 16.7 ns <SCLK <25 ns)—All values in this table are in nanoseconds
(continued)
Name
Description
CAS
SDWE
Column Address Select
SDRAM Write Enable
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
LDQM
Low Word SDRAM Data Mask
4.2 0.8 0.3 2.5 SCLK
HDQM
High Word SDRAM Data Mask
4.2 0.8 0.3 2.5 SCLK
SDA10
HBR
HBG
BOFF
BUSLOCK
BRST
BR7–0
FLYBY
IOEN
CPA 3, 4
DPA 3, 4
BMS5
FLAG3–06
SDRAM ADDR10
4.2 0.8 0.3 2.5 SCLK
Host Bus Request
2.8 0.5
SCLK
Host Bus Grant
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Back Off Request
2.8 0.5
SCLK
Bus Lock
4.2 0.8 0.3 2.5 SCLK
Burst pin
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Multiprocessing Bus Request pins 2.8 0.5 4.2 0.8
SCLK
FLYBY pin
4.2 0.8 0.3 2.5 SCLK
FLYBY pin
4.2 0.8 0.3 2.5 SCLK
Core Priority Access
2.8 0.5 5.8
2.5 SCLK
DMA Priority Access
2.8 0.5 5.8
2.5 SCLK
Boot Memory Select
4.2 0.8 0.3 2.5 SCLK
FLAG pins
4.2 1.0 1.0 4.0 SCLK
TMR0E5
RESET4, 7
Timer 0 Expired
Global Reset pin
4.2 1.0
SCLK
SCLK
TMS4
TDI4
Test Mode Select (JTAG)
Test Data Input (JTAG)
1.5 1.0
1.5 1.0
TCK
TCK
TDO
TRST4, 7, 9
BM5
EMU10
Test Data Output (JTAG)
Test Reset (JTAG)
Bus Master Debug aid only
Emulation
6.0 1.0 1.0 5.0 TCK_FE8
TCK
4.2 0.8
SCLK
5.5
5.0 TCK or
LCLK
JTAG_SYS_IN11
System input
1.5 11.0
TCK
JTAG_SYS_OUT12
ID2–09
System output
Chip ID – must be constant
16.0
TCK_FE8
CONTROLIMP2–09 Static pins – must be constant
DS2–09
Static pins – must be constant
LCLKRAT2–09
SCLKFREQ9
Static pins – must be constant
Static pins – must be constant
1 The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive
loading, see Figure 33 on Page 34.
2 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus
contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.
3 CPA and DPA pins are open drains and have 0.5 kΩ internal pull-ups.
4 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for
recognition in the current clock reference cycle.
5 This pin is a strap option. During reset, an internal resistor pulls the pin low.
6 For input specifications, see Table 17.
–26–
REV. A
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