ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices

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производитель

ADSP-TS101S
(Rev.:RevA)

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

7 For additional requirement details, see Reset and Booting on Page 8.

8 TCK_FE indicates TCK falling edge.

9 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.

10Reference clock depends on function.

11System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE,

CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN,

L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0, CONTROLIMP2–0, RESET, DMAR3–0.

12System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD,

SDCKE, SDWE, CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0,

L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT, L3DAT7–0, L3DIR, EMU.

REFERENCE

CLOCK

INPUT

SIGNAL

OUTPUT

SIGNAL

THREE-STATE

ASYNCHRONOUS

INPUT OR

OUTPUT

SIGNAL

1.5V

1.5V

INPUT

SETUP

INPUT

HOLD

OUTPUT

VALID

1.5V

OUTPUT

HOLD

OUTPUT

DISABLE

OUTPUT

ENABLE

1.5V

PULSEWIDTH

Figure 9. General AC Parameters Timing

REV. A

–27–

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