ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
ADSP-TS101S Datasheet PDF : 44 Pages
| |||
ADSP-TS101S
Table 22. AC Signal Specifications (for SCLK <16.7 ns)—All values in this table are in nanoseconds (continued)
Name
Description
CONTROLIMP2–09
DS2–09
LCLKRAT2–09
SCLKFREQ9
Static pins – must be constant
Static pins – must be constant
Static pins – must be constant
Static pins – must be constant
1 The output valid (max) value in this column applies for the standard 30 pF capacitive load used in testing. To see how output valid varies with capacitive
loading, see Figure 33 on Page 34.
2 The external port protocols employ bus IDLE cycles for bus mastership transitions as well as slave address boundary crossings to avoid any potential bus
contention. The apparent driver overlap, due to output disables being larger than output enables, is not actual.
3 CPA and DPA pins are open drains and have 0.5 kΩ internal pull-ups.
4 These input pins have Schmitt triggers and therefore do not need to be synchronized to a clock reference. These synchronous specifications only apply for
recognition in the current clock reference cycle.
5 This pin is a strap option. During reset, an internal resistor pulls the pin low.
6 For input specifications, see Table 17.
7 For additional requirement details, see Reset and Booting on Page 8.
8 TCK_FE indicates TCK falling edge.
9 These pins may change only during reset; recommend connecting it to VDD_IO/VSS.
10Reference clock depends on function.
11System inputs are: IRQ3–0, BMS, LCLKRAT2–0, SCLKFREQ, BM, TMR0E, FLAG3–0, ID2–0, BRST, WRH, WRL, RD, MSSD, SDCKE, SDWE,
CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, BOFF, HBR, ACK, BR7–0, L0CLKIN, L0DAT7–0, L1CLKIN, L1DAT7–0, L2CLKIN,
L2DAT7–0, L2DIR, L3CLKIN, L3DAT7–0, DS2–0, CONTROLIMP2–0, RESET, DMAR3–0.
12System outputs are: BMS, BM, BUSLOCK, TMR0E, FLAG3–0, FLYBY, IOEN, MSH, BRST, WRH, WRL, RD, MS1–0, HDQM, LDQM, MSSD,
SDCKE, SDWE, CAS, RAS, ADDR31–0, DATA63–0, DPA, CPA, HBG, ACK, BR7–0, L0CLKOUT, L0DAT7–0, L0DIR, L1CLKOUT, L1DAT7–0,
L1DIR, L2CLKOUT, L2DAT7–0, L2DIR, L3CLKOUT, L3DAT7–0, L3DIR, EMU.
Table 23. AC Signal Specifications (for 16.7 ns <SCLK <25 ns)—All values in this table are in nanoseconds
Name
ADDR31–0
DATA63–0
MSH
MSSD
MS1–0
RD
WRL
WRH
ACK
SDCKE
RAS
REV. A
Description
External Address Bus
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
External Data Bus
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Memory Select HOST Line
4.2 0.8 0.3 2.5 SCLK
Memory Select SDRAM Line
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Memory Select for Static Blocks
4.2 0.8 0.3 2.5 SCLK
Memory Read
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Write Low Word
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Write High Word
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Acknowledge for Data
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
SDRAM Clock Enable
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
Row Address Select
2.8 0.5 4.2 0.8 0.3 2.5 SCLK
–25–
Share Link: 