ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
Link Ports Data Transfer and Token Switch Timing
Table 24, Table 25, Table 26, and Table 27 with Figure 10,
Figure 11, Figure 12, and Figure 13 provide the timing specifi-
cations for the link ports data transfer and token switch.
Table 24. Link Ports—Transmit
Parameter
Timing Requirements
tCONNS1
tCONNS2
Connectivity Pulse Setup
Connectivity Pulse Setup
tCONNIW3
Connectivity Pulse Input Width
tACKS
Acknowledge Setup
Min
2 × tCCLK + 3.5
8
tLXCLK_TX + 1
0.5 × tLXCLK_TX
Max
Unit
ns
ns
ns
ns
Switching Characteristics
t4
LXCLK_TX
Transmit Link Clock Period
t1
LXCLKH_TX
t2
LXCLKH_TX
t1
LXCLKL_TX
t2
LXCLKL_TX
tDIRS
tDIRH
tDOS1
tDOH1
tDOS2
tDOH2
tLDOE
tLDOD5
Transmit Link Clock Width High
Transmit Link Clock Width High
Transmit Link Clock Width Low
Transmit Link Clock Width Low
LxDIR Transmit Setup
LxDIR Transmit Hold
LxDAT7–0 Output Setup
LxDAT7–0 Output Hold
LxDAT7–0 Output Setup
LxDAT7–0 Output Hold
LxDAT7–0 Output Enable
LxDAT7–0 Output Disable
0.9 × LR × 4 ns or
1.1 × LR × tCCLK
ns
0.9 × LR + tCCLK,
whichever is larger
0.33 × tLXCLK_TX
0.66 × tLXCLK_TX
ns
0.4 × tLXCLK_TX
0.6 × tLXCLK_TX
ns
0.33 × tLXCLK_TX
0.66 × tLXCLK_TX
ns
0.4 × tLXCLK_TX
0.6 × tLXCLK_TX
ns
0.5 × tLXCLK_TX
2 × tLXCLK_TX
ns
0.5 × tLXCLK_TX
2 × tLXCLK_TX
ns
0.25 × tLXCLK_TX – 1
ns
0.25 × tLXCLK_TX – 1
ns
0.17 × tLXCLK_TX – 1
ns
0.17 × tLXCLK_TX – 1
ns
1
ns
1
ns
1 The formula for this parameter applies when LR is 2. At 300 MHz, the ADSP-TS101S does not run at LR = × 2; the maximum LxCLK is 125 MHz.
2 The formula for this parameter applies when LR is 3, 4, or 8.
3 LxCLKIN shows the connectivity pulse with each of the three possible transitions to “Acknowledge.” After a connectivity pulse low minimum, LxCLKIN
may [1] return high and remain high for “Acknowledge,” [2] return high and subsequently go low (meeting tACKS) for “Not Acknowledge,” or [3] remain
low for “Not Acknowledge.”
4 The Link clock Ratio (LR) is 2, 3, 4, or 8 as set by the SPD bits in the LCTLx register.
5 This specification applies to the last data byte or the “Dummy” byte that follows the verification byte if enabled. For more information, see the ADSP-
TS101 TigerSHARC Processor Hardware Reference.
LxCLKOUT
LxCLKIN
LxDAT7–0
tDIRS
tCONNS
tLxCLK_Tx
tACKS
tLxCLKH_Tx
tLxCLKL_Tx
tDOS
tDOH
tDOS
tDOH
1
3
5
7
9
11
13
tDIRH
15
0
2
4
6
8
10
12
14
tCON NIW
tLDOE
tLDOD
LxDIR
Figure 10. Link Ports—Transmit
–28–
REV. A
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