ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-TS101S
(Rev.:RevA)

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

Power-Up Sequencing, Power-Up Reset, and Normal

Reset (Hot) Timing Requirements

For power-up sequencing, power-up reset, and normal reset (hot

reset) timing requirements, refer respectively to Table 19 and

Figure 6, Table 20 and Figure 7, and Table 21 and Figure 8.

Table 19. Power-Up Sequencing Timing

Parameter

Min

Timing Requirement

tVDD

VDD_IO Stable and Within Specification After VDD 0

and VDD_A are Stable and Within Specification

Max

Unit

ms

VDD

VDD_A

VDD_IO

tVDD

Figure 6. Power-Up Sequencing Timing

Table 20. Power-Up Reset Timing

Parameter

Min

Max

Unit

Timing Requirements

tSTART_LO

RESET Deasserted After VDD, VDD_A, VDD_IO,

2

ms

SCLK/LCLK, and Static/Strap Pins are Stable

and Within Specification

tPULSE1_HI

RESET Deasserted for First Pulse

50 × tSCLK

100 × tSCLK

ns

tPULSE2_LO

RESET Asserted for Second Pulse

100 × tSCLK

ns

tTRST_PWR1

TRST Asserted During Power-Up Reset

2 × tSCLK

ns

1 Applies after VDD, VDD_A, VDD_IO, and SCLK/LCLK and Static/Strap Pins are stable and within specification, and before RESET is deasserted.

RESET

TRST

VDD, VDD_A, VDD_IO,

SCLK/LCLK,

S TAT IC /STR A P

PINS

tSTART_LO

tPULSE1_HI

tPULSE2_LO

tTRST_PW R

Figure 7. Power-Up Reset Timing

–22–

REV. A

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