ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-TS101S
(Rev.:RevA)

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

TIMING SPECIFICATIONS

With the exception of Link Port, IRQ3–0, DMAR3–0, TMR0E,

FLAG3–0 (input), and TRST pins, all ac timing for the ADSP-

TS101S is relative to a reference clock edge. Because input

setup/hold, output valid/hold, and output enable/disable times

are relative to a clock edge, the timing data for the ADSP-TS101S

has few calculated (formula-based) values. For information on

ac timing, see General AC Timing. For information on link port

transfer timing, see Link Ports Data Transfer and Token Switch

Timing on Page 28.

General AC Timing

Timing is measured on signals when they cross the 1.5 V level as

described in Figure 9 on Page 27. All delays (in nanoseconds)

are measured between the point that the first signal reaches 1.5 V

and the point that the second signal reaches 1.5 V.

The ac asynchronous timing data for the IRQ3–0, DMAR3–0,

TMR0E, FLAG3–0 (input), and TRST pins appears in

Table 17.

The general ac timing data appears in Table 18, Table 22, and

Table 23. All ac specifications are measured with the load

specified in Figure 24 on Page 33, and with the output drive

strength set to strength 4. In order to calculate the output valid

and hold times for different load conditions and/or output drive

strengths, refer to Figure 25 on Page 33 through Figure 32 on

Page 34 (Rise and Fall Time vs. Load Capacitance) and

Figure 33 on Page 34 (Output Valid vs. Load Capacitance and

Drive Strength).

Table 17. AC Asynchronous Signal Specifications—All values in this table are in nanoseconds

Name

IRQ3–01

DMAR3–01

TMR0E

FLAG3–01, 2

TRST

Description

Interrupt request input

DMA request input

Timer 0 expired output

Flag pins input

JTAG test reset input

1 These input pins do not need to be synchronized to a clock reference.

2 For output specifications, see Table 22 and Table 23.

Pulsewidth Low (min)

tCCLK + 3 ns

tCCLK + 4 ns

3 × tCCLK ns

1 ns

Pulsewidth High (min)

tCCLK + 4 ns

4 × tSCLK ns

3 × tCCLK ns

Table 18. Reference Clocks

Signal

Type Description

Speed Clock

Grade Cycle

(MHz) Min (ns)

Clock

Cycle

Max (ns)

Clock

High

Min (ns)

Clock

Low

Min (ns)

Input

Jitter1

Tolerance

(ps)

CCLK2, 3

Core Clock

250

CCLK2, 3

Core Clock

300

LCLK_P4, 5, 6, 7 Input Local Clock

250

LCLK_P4, 5,6,7 Input Local Clock

300

SCLK_P5,7, 8, 9 Input System Clock,

All

SCLKFREQ = 1

TCK10

Input Test Clock (JTAG) All

4.0

12.5

3.3

12.5

Greater of 10

or CR × 4.0

CR × 12.5

{40% to 60% 100

Duty Cycle}

Greater of 10 CR × 12.5

or CR × (10÷3)

{40% to 60% 100

Duty Cycle}

Greater of 10 25

or CCLK × 2

{40% to 60% 100

Duty Cycle}

Greater of 30

12.5

12.5

or CCLK × 4

1 Actual input jitter should be combined with ac specifications for accurate timing analysis.

2 CCLK is the internal DSP clock or instruction cycle time. The period of this clock is equal to the Local Clock (LCLK_P) period divided by the Local

Clock Ratio (LCLKRAT2–0). For information on available internal DSP clock rates, see the ORDERING GUIDE on Page 43.

3 The period of CCLK is tCCLK.

4 The Core Clock Ratio (CR) is 2, 2.5, 3, 3.5, 4, 5, or 6 as set by the LCLKRAT2–0 pins. For more information, see Table 4 on Page 11.

5 See Clock Domains on Page 9.

6 The period of LCLK is tLCLK.

7 LCLK_P and SCLK_P must be connected to the same source.

8 For more information, see Table 3 on Page 11.

9 The period of SCLK is tSCLK.

10The period of TCK is tTCK.

REV. A

–21–

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