MT90222 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT90222 Datasheet PDF : 155 Pages
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MT90222/3/4
Pin Diagram - MT90222
The MT90222 uses a 384 pin PBGA with a 1.0 mm ball pitch.
Data Sheet
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1
A
DSTi[4] NC VDD5 NC NC RXSYN TXRing- TXRing- TXRing- sr_cs_1 sr_a[1] sr_a[4] VDD5 sr_a[7] sr_a sr_a sr_a VDD5 sr_d[6] NC TMS Reset NC NC
A
Ci[0] Data[1] Data[5] Sync
[11] [15] [18]
B
NC VSS RXSYN NC
IC
NC DSTi[0] TXRing- TXRing- TXRing- sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a sr_a sr_d[0] sr_d[3] sr_d[7] TDI TRST Test4 NC VSS NC
B
Ci[4]
Data[0] Data[4] Data[7]
[12] [16]
C
NC NC VSS RXCKi NC
IC RXCKi Latch TXRing- TXRing- VDD5 NC sr_a[2] sr_a[6] sr_a sr_a sr_a sr_d sr_d[4] Test3 TDO VDD5 NC VSS URx URx
C
[4]
[0]
Clk Data[2] Data[6]
[10] [14] [17]
[1]
Data[0] Data[2]
D
IC
NC NC VSS V3.3 NC VDD5 Test2 TXRing- V2.5 TXRing- sr_we V3.3 V2.5 sr_a[9] sr_a V3.3 sr_d[2] sr_d[5] TCK V3.3 VSS VSS URx URx URx
D
Data[3]
Clk
[13]
Data[1] Data[3] Data[4]
E
NC NC NC V3.3
VSS URx VDD5 URx
E
Data[5]
Data[6]
F VDD5 NC
IC
NC
V3.3 URx URx URx
F
Data[7] Data[8] Data[9]
G RXCKi DSTi[8] NC RXSYN
[8]
Ci[8]
URxD URxD URxD URxD G
ata[10] ata[11] ata[12] ata[13]
H VDD5 NC NC NC
URxD URxD URx VDD5 H
ata[14] ata[15] Par
J
NC
IC
IC
NC
URx URx NC VDD5 J
SOC Clav
K RXSYN NC
Ci[12]
NC V3.3
V2.5 URx- URx URxA K
CLK Enb ddr[0]
L
NC RXCKi DSTi NC
[12] [12]
VSS VSS VSS VSS VSS VSS
URxA URxA URxA URxA L
ddr[2] ddr[1] ddr[3] ddr[4]
M
NC
IC
NC NC
VSS VSS VSS VSS VSS VSS
UTx VDD5 UTx NC
M
Data[0]
Data[1]
N
NC VDD5 IC V2.5
VSS VSS VSS VSS VSS VSS
V3.3 UTx UTx UTx
N
Data[2] Data[3] Data[4]
P
NC NC NC V3.3
VSS VSS VSS VSS VSS VSS
V2.5 UTx VDD5 UTx
P
Data[6]
Data[5]
R
PD PD NC NC
VSS VSS VSS VSS VSS VSS
UTx UTxD UTxD UTxD R
Data[9] ata[10] ata[8] ata[7]
T
PD
PD
PD
NC
VSS VSS VSS VSS VSS VSS
UTxD VDD5 UTxD UTxD T
ata[13]
ata[12] ata[11]
U
PD DSTo TXCKio V2.5
[12] [12]
V3.3 UTxPar UTxD UTxD U
ata[15] ata[14]
V VDD5 TXSyn NC PD
cio[12]
UTxClk UTx UTx UTx
V
Enb Clav SOC
W
PD
NC
PD
PD
UTx UTx UTx UTx W
Addr[2] Addr[3] Addr[1] Addr[0]
Y
NC
PD
PD DSTo
[8]
UTx REFCK VDD5 NC
Y
Addr[4] [0]
AA TXCKio VDD5 TXSyn V3.3
[8]
cio[8]
REFCK REFCK NC REFCK AA
[2]
[3]
[1]
AB
NC
PD
PD VSS
V3.3 VDD5 PLL PLL AB
REF[1] REF[0]
AC
NC
PD
NC VSS V3.3 PD
NC VDD5 NC V3.3 RXRing RXRing V2.5 V3.3 up_a up_a[7] V2.5 up_irq NC up_d V3.3 VSS VSS NC
NC
Clk
AC
Data[7] Data[4]
[10]
[10]
AD
PD VDD5 VSS NC
NC
NC TXSyn PD
PD DSTo TXSyn VDD5 RXRing up_oe VDD5 up_a[6] up_a[3] up_a[0] up_d up_d up_d[8] up_d[5] up_d[2] VSS NC Test1 AD
cio[4]
[0] cio[0]
Data[1] or up_rd
[14] [11]
AE
NC VSS NC
NC
PD DSTo NC
NC
PD
NC RXRing RXRing RXRing up_cs up_a up_a[8] up_a[4] up_a[1] up_d up_d VDD5 up_d[6] up_d[4] up_d[1] VSS NC
AE
[4]
Data[6] Data[3] Data[0]
[11]
[15] [12]
AF
NC
NC
NC
NC TXCKio PD
PD
PD TXCKio RXRing RXRing RXRing RXRing up_r/w up_a[9] up_a[5] up_a[2] VDD5 up_d up_d[9] up_d[7] NC up_d[3] up_d[0]
AF
[4]
[0] Data[5] Data[2] Sync Clk
or
[13]
up_wr
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1
Figure 2 - MT90222 Pinout (Bottom View)
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Zarlink Semiconductor Inc.
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