MT90222 Просмотр технического описания (PDF) - Zarlink Semiconductor Inc
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MT90222 Datasheet PDF : 155 Pages
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MT90222/3/4
Pin Diagram - MT90223
The MT90223 uses a 384 pin PBGA with a 1.0 mm ball pitch.
Data Sheet
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1
A
DSTi[4] NC VDD5 DSTi[2] NC RXSYN TXRing- TXRing- TXRing- sr_cs_1 sr_a[1] sr_a[4] VDD5 sr_a[7] sr_a[11] sr_a[15] sr_a[18] VDD5 sr_d[6] NC TMS Reset NC NC
A
Ci[0] Data[1] Data[5] Sync
B
NC VSS RXSYN NC RXCKi NC DSTi[0] TXRing- TXRing- TXRing- sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a[12] sr_a[16] sr_d[0] sr_d[3] sr_d[7] TDI TRST Test4 NC VSS NC
B
Ci[4]
[2]
Data[0] Data[4] Data[7]
C
NC
NC VSS RXCKi NC RXSYN RXCKi Latch- TXRing- TXRing- VDD5 NC sr_a[2] sr_a[6] sr_a[10] sr_a[14] sr_a[17] sr_d[1] sr_d[4] Test3 TDO VDD5 NC VSS URx- URx-
C
[4]
Ci[2] [0]
Clk Data[2] Data[6]
Data[0] Data[2]
D RXSYN NC
Ci[6]
NC VSS V3.3 NC VDD5 Test2 TXRing- V2.5 TXRing- sr_we V3.3 V2.5 sr_a[9] sr_a[13] V3.3 sr_d[2] sr_d[5] TCK V3.3 VSS VSS URx- URx- URx- D
Data[3]
Clk
Data[1] Data[3] Data[4]
E DSTi[6] NC NC V3.3
VSS URx- VDD5 URx- E
Data[5]
Data[6]
F VDD5 NC RXCKi NC
[6]
V3.3 URx- URx- URx- F
Data[7] Data[8] Data[9]
G RXCKi DSTi[8] NC RXSYN
[8]
Ci[8]
H VDD5 NC NC NC
J
NC RXCKi RXSYN DSTi[10
[10] Ci[10] ]
URx- URx- URx- URx- G
Data[10 Data[11] Data[12 Data[13
]
]
]
URx- URx- URxPar VDD5 H
Data[14 Data[15
]
]
URx- URx- NC VDD5 J
SOC Clav
K RXSYN NC
Ci[12]
NC V3.3
V2.5 URxClk URxEnb URxA- K
ddr[0]
L
NC RXCKi DSTi[12 NC
[12]
]
VSS VSS VSS VSS VSS VSS
URxA- URxA- URxA- URxA- L
ddr[2] ddr[1] ddr[3] ddr[4]
M DSTi[14 RXSYN NC NC
] Ci[14]
VSS VSS VSS VSS VSS VSS
UTx- VDD5 UTx- NC
M
Data[0]
Data[1]
N
NC VDD5 RXCKi V2.5
[14]
VSS VSS VSS VSS VSS VSS
V3.3 UTx- UTx- UTx- N
Data[2] Data[3] Data[4]
P
NC NC NC V3.3
VSS VSS VSS VSS VSS VSS
V2.5 UTx- VDD5 UTx- P
Data[6]
Data[5]
R
PD
PD
NC DSTo[1
4]
T TXCKio TXSyn- PD NC
[14] cio[14]
U
PD DSTo[1 TXCKio V2.5
2]
[12]
V VDD5 TXSyn- NC PD
cio[12]
VSS VSS VSS VSS VSS VSS
VSS VSS VSS VSS VSS VSS
UTx- UTx- UTx- UTx- R
Data[9] Data[10 Data[8] Data[7]
]
UTx- VDD5 UTx- UTx-
T
Data[13
Data[12 Data[11]
]
]
V3.3 UTxPar UTx- UTx- U
Data[15 Data[14
]
]
UTxClk UTxEnb UTx- UTx- V
Clav SOC
W
PD DSTo[1 TXCKio TXSyn-
0]
[10] cio[10]
UTx- UTx- UTx- UTx- W
Addr[2] Addr[3] Addr[1] Addr[0]
Y
NC
PD
PD DSTo[8]
UTx- REFCK VDD5 NC
Y
Addr[4] [0]
AA TXCKio VDD5 TXSyn- V3.3
[8]
cio[8]
REFCK REFCK NC REFCK AA
[2]
[3]
[1]
AB
NC
PD
PD VSS
V3.3 VDD5 PLL- PLL- AB
REF[1] REF[0]
AC DSTo[6] TXCKio NC VSS V3.3 PD
NC VDD5 NC V3.3 RXRing RXRing V2.5 V3.3 up_a[10 up_a[7] V2.5 up_irq NC up_d[10 V3.3 VSS VSS NC
NC
Clk
AC
[6]
Data[7] Data[4]
]
]
AD TXSyn- VDD5 VSS NC
NC
NC TXSyn- PD TXSyn- DSTo[0] TXSyn- VDD5 RXRing up_oe VDD5 up_a[6] up_a[3] up_a[0] up_d[14 up_d[11 up_d[8] up_d[5] up_d[2] VSS NC Test1 AD
cio[6]
cio[4]
cio[2]
cio[0]
Data[1] or up_rd
]
]
AE
NC VSS NC
NC
PD DSTo[4] NC DSTo[2] PD
NC RXRing RXRing RXRing up_cs up_a[11 up_a[8] up_a[4] up_a[1] up_d[15 up_d[12 VDD5 up_d[6] up_d[4] up_d[1] VSS NC
AE
Data[6] Data[3] Data[0]
]
]
]
AF
NC NC NC NC TXCKio PD TXCKio PD TXCKio RXRing RXRing RXRing RXRing up_r/w up_a[9] up_a[5] up_a[2] VDD5 up_d[13 up_d[9] up_d[7] NC up_d[3] up_d[0]
AF
[4]
[2]
[0] Data[5] Data[2] Sync Clk
or
]
up_wr
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1
Figure 3 - MT90223 Pinout (Bottom View)
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Zarlink Semiconductor Inc.
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