E602204_HD64413A Просмотр технического описания (PDF) - Mitsumi

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E602204_HD64413A

SuperH RISC engine Peripheral LSI

Mitsumi 

5.3.1 Display Size Registers (DSR) .......................................................................... 234

5.3.2 Display Address Registers (DSAR).................................................................. 235

5.3.3 Display List Start Address Registers (DLSAR)................................................. 236

5.3.4 Multi-Valued Source Area Start Address Register (SSAR) ............................... 237

5.3.5 Work Area Start Address Register (WSAR) ..................................................... 238

5.3.6 Background Start Coordinate Registers (BGSR)............................................... 239

5.3.7 Video Area Start Address Registers (VSAR).................................................... 240

5.3.8 Video Window Size Registers (VSIZER) ......................................................... 242

5.3.9 Cursor Area Start Address Register (CSAR)..................................................... 243

5.3.10 Rendering Start Address Register (RSAR) ....................................................... 244

5.4 Display Control Registers............................................................................................. 244

5.4.1 Display Window Registers (DSWR) ................................................................ 245

5.4.2 Horizontal Sync Pulse Width Register (HSWR) ............................................... 247

5.4.3 Horizontal Scan Cycle Register (HCR) ............................................................ 247

5.4.4 Vertical Start Position Register (VSPR) ........................................................... 247

5.4.5 Vertical Scan Cycle Register (VCR) ................................................................ 248

5.4.6 Display Off Output Registers (DOOR)............................................................. 249

5.4.7 Color Detection Registers (CDER)................................................................... 250

5.4.8 Equalizing Pulse Width Register (EQWR) ....................................................... 250

5.4.9 Separation Width Register (SPWR).................................................................. 251

5.4.10 Video Display Start Position Registers (VPR) .................................................. 252

5.4.11 Cursor Display Start Position Registers (CSR) ................................................. 253

5.4.12 Color Palette Registers (CP000R to CP255R)................................................... 255

5.5 Rendering Control Registers......................................................................................... 257

5.5.1 Command Status Registers (CSTR).................................................................. 257

5.5.2 Current Pointer Registers (CURR) ................................................................... 258

5.5.3 Local Offset Registers (LCOR)........................................................................ 259

5.5.4 User Clipping Area Registers (UCLR) ............................................................. 259

5.5.5 System Clipping Area Registers (SCLR).......................................................... 261

5.5.6 Return Address Registers (RTNR) ................................................................... 261

5.5.7 Color Offset Register (COLOR)....................................................................... 262

5.6 Data Transfer Control Registers.................................................................................... 263

5.6.1 DMA Transfer Start Address Registers (DMASR) ........................................... 263

5.6.2 DMA Transfer Word Count Registers (DMAWR)............................................ 264

5.6.3 Image Data Transfer Start Address Registers (ISAR)........................................ 265

5.6.4 Image Data Size Registers (IDSR) ................................................................... 266

5.6.5 Image Data Entry Register (IDER)................................................................... 267

Section 6 Usage Notes....................................................................................269

6.1 Power-On Sequence ..................................................................................................... 269

6.2 Use of 64-Mbit SDRAM (×16 Type) ............................................................................ 270

6.3 CPU Interface Unit FIFO ............................................................................................. 271

6.4 Video Fetching Start Timing ........................................................................................ 272

Rev. 2.0, 09/02, page ix of xviii

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