E602204_HD64413A Просмотр технического описания (PDF) - Mitsumi

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E602204_HD64413A

SuperH RISC engine Peripheral LSI

Mitsumi 

Figures

Section 1 Overview

Figure 1.1 Sample System Configuration ...................................................................................1

Figure 1.2 Reduced System Size Through Use of UGM Architecture..........................................2

Figure 1.3 Unified System Bus Interface ....................................................................................3

Figure 1.4 Double-Buffering Architecture..................................................................................4

Figure 1.5 Graphics Accelerator.................................................................................................5

Figure 1.6 Pipeline Graphics Processing ....................................................................................5

Figure 1.7 Display Composite Function .....................................................................................6

Figure 1.8 Digital Video Images ................................................................................................6

Figure 1.9 Data Flow when Using a 3D Algorithm .....................................................................7

Figure 1.10 Internal Block Diagram .........................................................................................12

Figure 1.11 State Transition Diagram.......................................................................................13

Section 2 Pins

Figure 2.1 Pin Configuration....................................................................................................15

Figure 2.2 Pin Arrangement .....................................................................................................16

Figure 2.3 Example of Circuit for Connection of Pins CAP1 and CAP2....................................24

Figure 2.4 Connections of Bypass Capacitors between Power Supplies Near the Pins ...............25

Figure 2.5 Example of Circuit for Connection of REXT, CBU, and CBL Pins ..........................30

Figure 2.6 Example of Connection of Video Input Pins ............................................................31

Section 3 UGM Architecture

Figure 3.1 Example of System Configuration Using UGM .......................................................34

Figure 3.2 Example of UGM Mapping onto CPU Memory Space .............................................34

Figure 3.3 Byte Exchange Diagram..........................................................................................40

Figure 3.4 Image Data Specifications.......................................................................................41

Figure 3.5 Register Setting Procedure for ∆YUV/YUV-to-RGB Conversion.............................41

Figure 3.6 Example of Settings for Transferring 320 × 240 YUV Source Data to UGM

by Means of Four DMA Operations.........................................................................42

Figure 3.7 Configuration of One Memory Unit (512 Bytes) ......................................................52

Figure 3.8 UGM Address Transitions.......................................................................................53

Figure 3.9 Correspondence between UGM Physical Addresses (Bytes) and 2-Dimensinal

Virtual Addresses ...................................................................................................54

Figure 3.10 Work Address Space .............................................................................................55

Figure 3.11 Relationship between UGM Physical Addresses (Byte) and Work Addresses .........55

Figure 3.12 Sample Memory Map

(Corresponding to 640 × 480 Screen Size, with 16 Bits/Pixel ) ...............................57

Figure 3.13 Relationship between 8-Bits/Pixel and 16-Bits/Pixel Memory Maps.......................58

Figure 3.14 Example of Frame Buffer FB1 Location When HDIS = 1 ......................................59

Figure 3.15 Screen Coordinates ...............................................................................................60

Figure 3.16 Rendering Coordinates ..........................................................................................62

Rev. 2.0, 09/02, page xiii of xviii

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