E602204_HD64413A Просмотр технического описания (PDF) - Mitsumi

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E602204_HD64413A

SuperH RISC engine Peripheral LSI

Mitsumi 

Figure 3.17 Multi-Valued Source Coordinates (LNi = 0) .......................................................... 64

Figure 3.18 Multi-Valued Source Coordinates with LNi = 1 Specified (Linear Address)........... 64

Figure 3.19 Binary Source Coordinates.................................................................................... 65

Figure 3.20 Work Coordinates ................................................................................................. 66

Figure 3.21 Operation in Auto Display Change Mode .............................................................. 69

Figure 3.22 Operation in Auto Rendering Mode....................................................................... 70

Figure 3.23 Operation in Manual Display Change Mode .......................................................... 72

Figure 3.24 Operation when Using VBKEM Command ........................................................... 73

Figure 3.25 Display Timing..................................................................................................... 75

Figure 3.26 Configuration of the Display Screen for Q2SD ...................................................... 78

Figure 3.27 Example of Background Screen Simple Scroll (WRAP = 0)................................... 80

Figure 3.28 Example of Background Screen Wraparound Scroll (WRAP = 1) .......................... 81

Figure 3.29 Examples of Raster Scan Control Display.............................................................. 82

Figure 3.30 Display by Interlace Sync Method......................................................................... 84

Figure 3.31 Display by Non-Interlace Method.......................................................................... 85

Figure 3.32 Non-Interlace Mode Display Output...................................................................... 86

Figure 3.33 Interlace Mode Display Output.............................................................................. 87

Figure 3.34 (1) Interlace Sync & Video Mode Output .............................................................. 88

Figure 3.34 (2) Interlace Sync & Video Mode Output .............................................................. 89

Figure 3.35 Signal Flow in TV Sync Mode .............................................................................. 91

Figure 3.36 Display Timing..................................................................................................... 93

Figure 3.37 &6<1& Output Waveform.................................................................................... 94

Figure 3.38 Drawing Functions................................................................................................98

Figure 3.39 Example of POLYGON4 Transfer Data Combinations .......................................... 99

Figure 3.40 Multi-Valued Source Data Configuration ............................................................ 100

Figure 3.41 Example of Kanji Font as Binary Source (TDX = 24, TDY = 24)......................... 100

Figure 3.42 Binary Work Data Configuration......................................................................... 101

Figure 3.43 Rendering Attribute Bit Arrangement .................................................................. 102

Figure 3.44 Example of Source Style Specification ................................................................ 103

Figure 3.45 Example of Clipping Specification ...................................................................... 104

Figure 3.46 Examples of Even/Odd Select Specifications....................................................... 105

Figure 3.47 Examples of Bold Line Drawing ......................................................................... 107

Figure 3.48 Example of Display List...................................................................................... 111

Figure 3.49 Example of Timing for Suspending and Resuming Background Screen Drawing.. 112

Figure 3.50 Updating of Q2SD’s Internal Buffers................................................................... 113

Figure 3.51 Video Incorporation Signals................................................................................ 115

Figure 3.52 Video Capture Timing ........................................................................................ 115

Figure 3.53 Capture State ...................................................................................................... 116

Figure 3.54 Display State....................................................................................................... 116

Figure 3.55 Video Screen Area .............................................................................................. 118

Figure 3.56 Interlace Capture................................................................................................. 119

Figure 3.57 Interlace Composite Capture ............................................................................... 119

Figure 3.58 Interlace Capture (Odd Field).............................................................................. 120

Rev. 2.0, 09/02, page xiv of xviii

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