E602204_HD64413A Просмотр технического описания (PDF) - Mitsumi

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E602204_HD64413A

SuperH RISC engine Peripheral LSI

Mitsumi 

Tables

Section 1 Overview

Table 1.1 A List of Specifications ............................................................................................9

Table 1.2 Pin States After Reset .............................................................................................14

Section 2 Pins

Table 2.1 Pin Functions .........................................................................................................17

Table 2.2 Operating Mode Selection ......................................................................................23

Table 2.3 Input Clocks and Operating Frequencies .................................................................24

Section 3 UGM Architecture

Table 3.1 Registers with Internal Update Function..................................................................38

Table 3.2 Interrupt Output Function .......................................................................................51

Table 3.3 Setting for Number of Refreshes .............................................................................74

Table 3.4 Sample Estimations of Number of Refresh Cycles...................................................74

Table 3.5 Variables Defined by Display Screen ......................................................................76

Table 3.6 Register Settings.....................................................................................................77

Table 3.7 Background Screen Related Register Settings .........................................................80

Table 3.8 Combinations of Q2SD Output and Monitor Input Methods ....................................85

Table 3.9 Drawing Commands...............................................................................................96

Table 3.10 Bold Line Drawing Settings ..............................................................................106

Table 3.11 8-Bit Pixel Interface..........................................................................................126

Table 3.12 Selecting Modes of Video Capture and Display for the Q2SD ...........................134

Section 4 Display List

Table 4.1 Command List......................................................................................................137

Section 5 Registers

Table 5.1 Registers ..............................................................................................................199

Table 5.2 Bit Configuration..................................................................................................226

Table 5.3 YUV Mode Setting...............................................................................................229

Table 5.4 Video Incorporation Reduction Ratio....................................................................233

Appendix G Example of Display Control

Table G.1 Setting Example of Variables ((TVM1,0) = (0,0), (SCM1,0) = (0,0)) .................337

Table G.2 Register Setting Example ((TVM1,0) = (0,0), (SCM1,0) = (0,0)) .......................337

Table G.3 Setting Example of Variables ((TVM1,0) = (0,0), (SCM1,0) = (1,1)) .................339

Table G.4 Register Setting Example ((TVM1,0) = (0,0), (SCM1,0) = (1,1)) .......................339

Appendix H Example of Drawing Control

Table H.1 Relationship of DBF and Display Screen (FG) ..................................................342

Rev. 2.0, 09/02, page xvii of xviii

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