E602204_HD64413A Просмотр технического описания (PDF) - Mitsumi

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E602204_HD64413A

SuperH RISC engine Peripheral LSI

Mitsumi 

Figure 3.59 Interlace Capture (Even Field).............................................................................120

Figure 3.60 Interlace Video Input Field Handling Specification ..............................................121

Figure 3.61 Reducing the Size of the Captured Image.............................................................122

Figure 3.62 Incorrect Settings for the Reduction Ratios ..........................................................123

Figure 3.63 Setting up the Capture Area.................................................................................124

Figure 3.64 Example of the Settings for Capture Areas...........................................................125

Figure 3.65 The Flow of YCbCr (4:2:2) Data .........................................................................126

Figure 3.66 YCbCr (4:2:2) Data Format.................................................................................127

Figure 3.67 Conversion of YCbCr Data into RGB Format ......................................................128

Figure 3.68 The RGB Data Format (16 Bits/Pixel) .................................................................128

Figure 3.69 Position of the Video Image ................................................................................129

Figure 3.70 The Display of Data Captured in Interlace Mode and Display ..............................130

Figure 3.71 The Display of Data Captured in the Interlace Composite Mode...........................131

Figure 3.72 The Display of Data Captured in the Interlace Odd-Only Mode...........................132

Figure 3.73 The Display of Data Captured in the Interlace Even-Only Mode...........................133

Section 6 Usage Notes

Figure 6.1 Power-On Sequence..............................................................................................269

Figure 6.2 Video Interface Timing .........................................................................................272

Section 7 Electrical Characteristics

Figure 7.1 Basis of VOL Timing Testing .................................................................................276

Figure 7.2 Test Load Circuit ..................................................................................................277

Figure 7.3 Input Clocks..........................................................................................................288

Figure 7.4 Reset Timing ........................................................................................................288

Figure 7.5 CPU Read Cycle Timing (CPU ← Q2SD) with Hardware Wait .............................289

Figure 7.6 CPU Read Cycle Timing (CPU → Q2SD) with Hardware Wait .............................290

Figure 7.7 (1) DMA Write Cycle Timing (Single Address, DMAC → Q2SD) ........................291

Figure 7.7 (2) DMA Write Cycle Timing (Single Address, DMAC → Q2SD) ........................292

Figure 7.7 (3) DMA Write Cycle Timing (Dual Address, DMAC → Q2SD)...........................293

Figure 7.7 (4) DMA Write Cycle Timing (Dual Address, DMAC → Q2SD)...........................294

Figure 7.8 Interrupt Output Timing ........................................................................................295

Figure 7.9 UGM Read Cycle Timing .....................................................................................296

Figure 7.10 UGM Write Cycle Timing...................................................................................297

Figure 7.11 (1) UGM Refresh Cycle Timing ..........................................................................298

Figure 7.11 (2) UGM Mode Register Setting Cycle Timing....................................................299

Figure 7.12 Master Mode Display Timing..............................................................................300

Figure 7.13 (1) TV Sync Mode Display Timing .....................................................................301

Figure 7.13 (2) TV Sync Mode Display Timing .....................................................................302

Figure 7.14 (1) Video Interface Timing..................................................................................303

Figure 7.14 (2) Video Interface Timing..................................................................................303

Appendix C Drawing Algorithms

Figure C.1 Two Representations of a Straight Line on a Raster Display..................................316

Rev. 2.0, 09/02, page xv of xviii

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