ADSP-BF539F(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-BF539F Datasheet PDF : 60 Pages
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ADSP-BF539/ADSP-BF539F
Capacitive Loading
12
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 42). VLOAD is 1.5 V for VDDEXT
(nominal) = 3.3 V. Figure 43 on Page 53 through Figure 52 on
10
Page 54 show how output rise and fall times vary with capaci-
tance. The delay and hold specifications given should be de-
8
rated by a factor derived from these figures. The graphs in these
figures may not be linear outside the ranges shown.
6
RISE TIME
FALL TIME
14
12
RISE TIME
10
FALL TIME
8
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 43. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 2.7 V (MIN)
12
10
RISE TIME
8
FALL TIME
6
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 44. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver A at VDDEXT = 3.65 V (MAX)
4
2
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 45. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 2.7 V (MIN)
10
9
8
RISE TIME
7
6
FALL TIME
5
4
3
2
1
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 46. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver B at VDDEXT = 3.65 V (MAX)
30
25
RISE TIME
20
15
FALL TIME
10
5
0
0
50
100
150
200
250
LOAD CAPACITANCE (pF)
Figure 47. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
Driver C at VDDEXT = 2.7 V (MIN)
Rev. A | Page 53 of 60 | February 2008
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