ADSP-BF539F(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-BF539F
(Rev.:RevA)

Blackfin Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

POWER DISSIPATION

Many operating conditions can affect power dissipation. System

designers should refer to Estimating Power for ADSP-

BF538/ADSP-BF539 Blackfin Processors (EE-298) on the Analog

Devices, Inc. website (www.analog.com)—use site search on

“EE-298.” This document provides detailed information for

optimizing your design for lowest power.

See the ADSP-BF539/BF539F Blackfin Processor Hardware Ref-

erence Manual for definitions of the various operating modes

and for instructions on how to minimize system power.

TEST CONDITIONS

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 40

shows the measurement point for ac measurements (except out-

put enable/disable). The measurement point VMEAS is 1.5 V for

VDDEXT (nominal) = 3.3 V.

INPUT

OR

VMEAS

OUTPUT

VMEAS

Figure 40. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Output Enable Time Measurement

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

The output enable time tENA is the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of Fig-

ure 41, “Output Enable/Disable,” on Page 52.

The time tENA_MEASURED is the interval, from when the reference

signal switches, to when the output voltage reaches VTRIP(high)

or VTRIP(low). VTRIP(high) is 2.0 V and VTRIP(low) is 1.0 V for

VDDEXT (nominal) = 3.3 V. Time tTRIP is the interval from when

the output starts driving to when the output reaches the

VTRIP(high) or VTRIP(low) trip voltage.

Time tENA is calculated as shown in the equation:

tENA = tENA_MEASURED – tTRIP

If multiple pins (such as the data bus) are enabled, the measure-

ment value is that of the first pin to start driving.

Output Disable Time Measurement

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time tDIS is the

difference between tDIS_MEASURED and tDECAY as shown on the left

side of Figure 41.

tDIS = tDIS_MEASURED – tDECAY

The time for the voltage on the bus to decay by ΔV is dependent

on the capacitive load CL and the load current IL. This decay

time can be approximated by the equation:

tDECAY = (CLΔV) ⁄ IL

The time tDECAY is calculated with test loads CL and IL, and with

ΔV equal to 0.5 V for VDDEXT (nominal) = 3.3 V.

The time tDIS+_MEASURED is the interval from when the reference

signal switches, to when the output voltage decays ΔV from the

measured output high or output low voltage.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate tDECAY using the equation given above. Choose ΔV

to be the difference between the ADSP-BF539/ADSP-BF539F

processor output voltage and the input threshold for the device

requiring the hold time. CL is the total bus capacitance (per data

line), and IL is the total leakage or three-state current (per data

line). The hold time will be tDECAY plus the various output dis-

able times as specified in the Timing Specifications on Page 29

(for example tDSDAT for an SDRAM write cycle as shown in

Table 21 on Page 35).

tDIS

VOH

(MEASURED)

VOL

(MEASURED)

REFERENCE

SIGNAL

tDIS_MEASURED

tENA

VOH (MEASURED) 2 DV

VOL (MEASURED) + DV

tDECAY

tENA_MEASURED

VOH(MEASURED)

VTRIP(HIGH)

VTRIP(LOW)

VOL(MEASURED)

tTRIP

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

HIGH IMPEDANCE STATE

Figure 41. Output Enable/Disable

TO

OUTPUT

PIN

50⍀

30pF

VLOAD

Figure 42. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

Rev. A | Page 52 of 60 | February 2008

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