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ADSP-BF539F(RevA) Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге
Компоненты Описание
производитель
ADSP-BF539F
(Rev.:RevA)
ADI
Analog Devices ADI
ADSP-BF539F Datasheet PDF : 60 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
ADSP-BF539/ADSP-BF539F
Serial Ports Timing
Table 25 through Table 28 on Page 42 and Figure 23 on Page 42
through Figure 24 on Page 43 describe Serial Port operations.
Table 25. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
3.0
ns
tHFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
3.0
ns
tSDRE
Receive Data Setup Before RSCLKx1
tHDRE
Receive Data Hold After RSCLKx1
3.0
ns
3.0
ns
tSCLKEW
TSCLKx/RSCLKx Width
4.5
ns
tSCLKE
TSCLKx/RSCLKx Period
15.0
ns
Switching Characteristics
tDFSE
tHOFSE
tDDTE
tHDTE
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
Transmit Data Delay After TSCLKx2
Transmit Data Hold After TSCLKx2
10.0
ns
0.0
ns
10.0
ns
0.0
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 26. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
8.0
ns
tHFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Externally Generated TFSx/RFSx)1
–1.5
ns
tSDRI
Receive Data Setup Before RSCLKx1
8.0
ns
tHDRI
Receive Data Hold After RSCLKx1
–1.5
ns
tSCLKEW
TSCLKx/RSCLKx Width
4.5
ns
tSCLKE
TSCLKx/RSCLKx Period
15.0
ns
Switching Characteristics
tDFSI
tHOFSI
tDDTI
tHDTI
tSCLKIW
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)2
Transmit Data Delay After TSCLKx2
Transmit Data Hold After TSCLKx2
TSCLKx/RSCLKx Width
3.0
ns
–1.0
ns
3.0
ns
–2.0
ns
4.5
ns
1 Referenced to sample edge.
2 Referenced to drive edge.
Table 27. Serial Ports—Enable and Three-State
Parameter
Switching Characteristics
tDTENE
tDDTTE
tDTENI
tDDTTI
Data Enable Delay from External TSCLKx1
Data Disable Delay from External TSCLKx1
Data Enable Delay from Internal TSCLKx1
Data Disable Delay from Internal TSCLKx1
1 Referenced to drive edge.
Min
Max
Unit
0
ns
10.0
ns
–2.0
ns
3.0
ns
Rev. A | Page 41 of 60 | February 2008

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