DS2151 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS2151

T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

TCR2: TRANSMIT CONTROL REGISTER 2 (Address=36 Hex)

(MSB)

TEST1 TEST0 TZBTSI TSDW

TSM

TSIO

TD4YM

DS2151Q

(LSB)

B7ZS

SYMBOL

TEST1

POSITION NAME AND DESCRIPTION

TCR2.7 Test Mode Bit 1 for Output Pins. See Table 3-1.

TEST0

TCR2.6 Test Mode Bit 0 for Output Pins. See Table 3-1.

TZBTSI

TCR2.5

Transmit Side ZBTSI Enable.

0=ZBTSI disabled

1=ZBTSI enabled

TSDW

TCR2.4

TSYNC Double-Wide. (note: this bit must be set to 0 when

TCR2.3=1 or when TCR2.2=0)

0=do not pulse double-wide in signaling frames

1=do pulse double-wide in signaling frames

TSM

TCR2.3

TSYNC Mode Select.

0=frame mode (see the timing in Section 13)

1=multiframe mode (see the timing in Section 13)

TSIO

TCR2.2

TSYNC I/O Select.

0=TSYNC is an input

1=TSYNC is an output

TD4YM

TCR2.1

Transmit Side D4 Yellow Alarm Select.

0=0s in bit 2 of all channels

1=a 1 in the S-bit position of frame 12

B7ZS

XTCR2.0

Bit 7 0 Suppression Enable.

0=no stuffing occurs

1=Bit 7 force to a 1 in channels with all 0s

OUTPUT PIN TEST MODES Table 3-1

TEST1

TEST0

EFFECT ON OUTPUT PINS

0

0

operate normally

0

1

force all output pins 3-state (including all I/O pins and parallel port pins)

1

0

force all output pins low (including all I/O pins except parallel port pins)

1

1

force all output pins high (including all I/O pins except parallel port pins)

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