DS2151 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

Номер в каталоге

Компоненты Описание

производитель

DS2151

T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

CCR3: COMMON CONTROL REGISTER 3 (Address=30 Hex)

(MSB)

ESMDM

ESR

P16F

RSMS

PDE

TLD

TLU

DS2151Q

(LSB)

LIRST

SYMBOL

ESMDM

POSITION

CCR3.7

NAME AND DESCRIPTION

Elastic Store Minimum Delay Mode. See Section 10.3 for

details.

0=elastic stores operate at full two-frame depth

1=elastic stores operate at 32-bit depth

ESR CCR3.6 Elastic Store Reset. Setting this bit from a 0 to a 1 will force

the elastic stores to a known depth. Should be toggled after

SYSCLK has been applied and is stable. Must be cleared and

set again for a subsequent reset.

P16F

CCR3.5

Function of Pin 16.

0=Receive Loss of Sync (RLOS).

1=Loss of Transmit Clock (LOTC).

RSMS

CCR3.4

RSYNC Multiframe Skip Control. Useful in framing format

conversions from D4 to ESF.

0=RSYNC will output a pulse at every multiframe

1=RSYNC will output a pulse at every other multiframe note:

for this bit to have any affect, the RSYNC must be set to output

multiframe pulses (RCR2.4=1 and RCR2.3=0) and the receive

elastic store must be bypassed. (CCR1.2 = 0).

PDE CCR3.3 Pulse Density Enforcer Enable.

0=disable transmit pulse density enforcer

1=enable transmit pulse density enforcer

TLD CCR3.2 Transmit Loop Down Code (001).

0=transmit data normally

1=replace normal transmitted data with Loop Down code

TLU CCR3.1 Transmit Loop Up Code (00001).

0=transmit data normally

1=replace normal transmitted data with Loop Up code

LIRST

CCR3.0

Line Interface Reset. Setting this bit from a 0 to a one will

initiate an internal reset that affects the slicer, AGC, clock

recovery state machine and jitter attenuator. Normally this bit is

only toggled on power-up. Must be cleared and set again for a

subsequent reset.

LOOP CODE GENERATION

When either the CCR3.1 or CCR3.2 bits are set to 1, the DS2151Q will replace the normal transmitted

payload with either the Loop Up or Loop Down code respectively. The DS2151Q will overwrite the

repeating loop code pattern with the framing bits. The SCT will continue to transmit the loop codes as

long as either bit is set. It is an illegal state to have both CCR3.1 and CCR3.2 set to 1 at the same time.

15 of 51

Share Link: