DS2151 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2151

T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

RIR2: RECEIVE INFORMATION REGISTER 2 (Address=31 Hex)

(MSB)

RL1

RL0

TESF

TESE

TSLIP

JALT

RPDV

DS2151Q

(LSB)

TPDV

SYMBOL POSITION NAME AND DESCRIPTION

RL1 RIR2.7 Receive Level Bit 1. See Table 4-1.

RL0 RIR2.6 Receive Level Bit 0. See Table 4-1.

TESF RIR2.5 Transmit Elastic Store Full. Set when the transmit elastic

store buffer fills and a frame is deleted.

TESE RIR2.4 Transmit Elastic Store Empty. Set when the transmit elastic

store buffer empties and a frame is repeated.

TSLIP RIR2.3 Transmit Elastic Store Slip Occurrence. Set when the

transmit elastic store has either repeated or deleted a frame.

JALT

RIR2.2

Jitter Attenuator Limit Trip. Set when the jitter attenuator

FIFO reaches to within 4 bits of its limit; useful for debugging

jitter attenuation operation.

RPDV

RIR2.1

Receive Pulse Density Violation. Set when the receive data

stream does not meet the ANSI T1.403 requirements for pulse

density.

TPDV

RIR2.0

Transmit Pulse Density Violation. Set when the transmit data

stream does not meet the ANSI T1.403 requirements for pulse

density.

DS2151Q RECEIVE T1 LEVEL INDICATION Table 4-1

RL1

RL0

TYPICAL LEVEL RECEIVED

0

0

+2 dB to -7.5 dB

0

1

-7.5 dB to -15 dB

1

0

-15 dB to -22.5 dB

1

1

less than -22.5 Db

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