DS2151 Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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производитель

DS2151

T1 Single-Chip Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2151Q

from the interrupt pins via the Interrupt Mask Register 1 (IMR1) and Interrupt Mask Register 2 (IMR2)

respectively.

RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)

(MSB)

COFA

8ZD

16ZD

RESF

RESE

SEFE

B8ZS

(LSB)

FBE

SYMBOL POSITION NAME AND DESCRIPTION

COFA RIR1.7 Change of Frame Alignment. Set when the last resync

resulted in a change of frame or multiframe alignment.

8ZD RIR1.6 Eight 0 Detect. Set when a string of eight consecutive 0s have

been received at RPOS and RNEG.

16ZD RIR1.5 Sixteen 0 Detect. Set when a string of 16 consecutive 0s have

been received at RPOS and RNEG.

RESF RIR1.4 Receive Elastic Store Full. Set when the receive elastic store

buffer fills and a frame is deleted.

RESE RIR1.3 Receive Elastic Store Empty. Set when the receive elastic

store buffer empties and a frame is repeated.

SEFE RIR1.2 Severely Errored Framing Event. Set when 2 out of 6

framing bits (Ft or FPS) are received in error.

B8ZS

RIR1.1

B8ZS Code Word Detect. Set when a B8ZS code word is

detected at RPOS and RNEG independent of whether the B8ZS

mode is selected or not via CCR2.6.

FBE RIR1.0 Frame Bit Error. Set when a Ft (D4) or FPS (ESF) framing

bit is received in error.

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