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EN5394QI

9A PowerSoC Voltage Mode Synchronous Buck PWM DC-DC Converter With Integrated Inductor

Altera Corporation 

EN5394QI

Electrical Characteristics table. See Figures 6 be used advantageously for power supply

and 7 for an example of using phase delay.

sequencing using the precision Enable threshold.

Margining

Using MAR1 and MAR2 pins, the nominal output

voltage can be increased / decreased by 2.5, 5

or 10% for system compliance, reliability or other

tests. The POK threshold voltages scale with the

margined output voltages. The following table

provides the possible combinations:

MAR1 MAR2 Output Modulation

Float Float

0%

Low

Low

-2.5%

High

Low

+2.5%

Low

High

-5%

High High

+5%

Low Float

-10%

High Float

+10%

Float High

0%, Delay Bypass

Float Low

Reserved

Note: Low means tie to GND. High means tie to VIN

as shown in Figure 5.

As shown above, when MAR1 is floating, and

MAR2 is high, the device enters the delay

bypass mode. In this mode, the delay from the

internal clock or S_IN to S_OUT is almost

eliminated (see Electrical Characteristics table).

Soft-Start Operation

The SS pin in conjunction with a small external

capacitor between this pin and AGND provides

the soft start function to limit the in-rush current

during start-up. During start-up of the converter

the reference voltage to the error amplifier is

gradually increased to its final level as an internal

current source of typically 10uA charges the soft

start capacitor. The typical soft-start time for the

output to reach regulation voltage, from when

AVIN > VUVLO and ENABLE crosses its logic high

threshold, is given by:

TSS = (CSS * 65KΩ) ± 25%

where the soft-start time TSS is in seconds and

the soft-start capacitance CSS is in Farads.

Typically, around 15nF is recommended. The

soft-start capacitor should be between 4.7nF and

100nF. A proper choice of SS capacitance can

During a soft-start cycle, when the soft-start

capacitor voltage reaches 0.60V, the output has

reached its programmed regulation range. Note

that the soft-start current source will continue to

charge the SS capacitor beyond 0.6V. During

normal operation, the soft-start capacitor will

charge to a final value of ~1.5V.

Soft-Shutdown Operation

When the Enable signal is de-asserted, the soft-

start capacitor is discharged in a controlled

manner. Thus the output voltage ramps down

gradually. The internal circuits are kept active for

the duration of soft-shutdown, thereafter they are

deactivated.

Pre-Bias Operation

When EN_PB is asserted, the device will support

a monotonic output voltage ramp if the output

capacitor is charged to a pre-bias level.

Proprietary circuit ensures the output voltage

ramps monotonically from pre-bias voltage to the

programmed output voltage. Monotonic start-up

is guaranteed by design for pre-bias voltages

between 20% and 85% of the programmed

output voltage. This feature is not supported

when ENABLE is tied to VIN.

POK Operation

The POK signal indicates if the output voltage is

within a specified range. The POK signal is

asserted when the rising output voltage crosses

92% (nominal) of the programmed output

voltage. POK is de-asserted ~50us (256 clock

cycles) after the falling output voltage crosses

90% (nominal) of the programmed voltage. POK

is also de-asserted if the output voltage exceeds

120% of the programmed output. If the feedback

loop is broken, POK will remain de-asserted

(output < 92% of programmed value), and the

output voltage will equal the input voltage. If

however, there is a short across the PFET, and

the feedback is in place, POK will be de-asserted

as an over voltage condition. The power NFET is

also turned on, resulting in a large input supply

current. This in turn is expected to trip the OCP

03738

11

October 11, 2013

www.altera.com/enpirion

Rev E

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