EN5394QI Просмотр технического описания (PDF) - Altera Corporation
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EN5394QI
Altera Corporation
EN5394QI Datasheet PDF : 19 Pages
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of the EN5394QI input power supply.
POK is an open drain output. It requires an
external pull up. Multiple EN5394QI’s POK pins
may be connected to a single pull up. The open
drain NFET is designed to sink up to 4mA. The
pull-up resistor value should be chosen
accordingly for when POK is logic low.
Input Under-Voltage Lock-Out (UVLO)
When the input voltage is below a required
voltage level (VUVLO) for normal operation, the
converter switching is inhibited. The lock-out
threshold has hysteresis to prevent chatter.
UVLO is implemented to ensure that operation
does not begin before there is adequate voltage
to properly bias all internal circuitry.
Over-Current Protection (OCP)
The current limit and short-circuit protection is
achieved by sensing the current flowing through
a sense P-FET. When the sensed current
exceeds the current limit, both NFET and PFET
switches are turned off. If the over-current
condition is removed, the over-current protection
circuit will re-enable the PWM operation. If the
over-current condition persists, the circuit will
continue to protect the device.
The OCP trip point is nominally set to 150% of
maximum rated load. In the event the OCP circuit
trips, the device enters a hiccup mode. The
device is disabled for ~10msec and restarted
with a normal soft-start. This cycle can continue
indefinitely as long as the over current condition
persists. During soft-start at power up or fault
EN5394QI
recovery, the hiccup mode is disabled and the
device has cycle-by-cycle current limiting. Tie
OCP_ADJ pin to GND for proper OCP operation.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approximately 20ºC, the converter will re-start
with a normal soft-start.
Compensation
The EN5394 uses of a type III compensation
network. Most of this network is integrated.
However a phase lead capacitor is required in
parallel with upper resistor of the external divider
network (see Figure 4). This network results in a
wide loop bandwidth and excellent load transient
performance. It is optimized for approximately
100μF of output filter capacitance at the voltage
sensing point. Additional decoupling capacitance
may be placed beyond the voltage sensing point
outside the control loop. Voltage-mode operation
provides high noise immunity at light load.
Further, voltage-mode control provides superior
impedance matching to ICs processed in sub
90nm technologies.
In exceptional cases modifications to the
compensation may be required. The EN5394QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact Altera
Power Applications support.
Application Information
Output Voltage Programming
The EN5394 output voltage is determined by the
voltage presented at the VFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to VFB. A phase
lead capacitor CA is also required for stabilizing
the loop. Figure 4 shows the required
components and the equations to calculate their
values. Please note the equations below are
written to optimize the control loop as a function
of input voltage.
VOUT
RA
RB
RA = 30,000 ×Vin (value in Ω)
CA
CA
=
5.6 ×10−6
RA
(CA /R A in F/Ω)
Round CA down to closest
VFB
standard value lower than
calculated value.
RB
= VFB × RA
(VOUT − VFB )
VFB is 0.6V
nominal
Figure 4: Output voltage resistor divider and phase-
03738
12
October 11, 2013
www.altera.com/enpirion
Rev E
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