EN5394QI Просмотр технического описания (PDF) - Altera Corporation
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EN5394QI
Altera Corporation
EN5394QI Datasheet PDF : 19 Pages
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lead capacitor calculation. The equations need to be
followed in the order written above.
Input Capacitor Selection
The EN5394QI requires between 30-40uF of
input capacitance. Low ESR ceramic capacitors
are required with X5R or X7R dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and
bias voltage.
In some applications, lower value ceramic
capacitors may be needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
Recommended Input Capacitors
Description
10uF, 10V, 10%
X7R, 1206
(3-4 capacitorsneeded)
22uF, 10V, 20%
X5R, 1206
(2 capacitorsneeded)
47uF, 6.3V, 20%
X5R, 1206
(1 capacitor needed)
MFG
Murata
Taiyo Yuden
Murata
Taiyo Yuden
Murata
Taiyo Yuden
P/N
GRM31CR71A106KA01L
LMK316B7106KL-T
GRM31CR61A226ME19L
LMK316BJ226ML-T
GRM31CR60J476ME19L
JMK212BJ476ML-T
Output Capacitor Selection
The EN5394 has been optimized for use with
about 100µF of output filter capacitance.
Additional capacitance may be placed beyond
the voltage sensing point outside the control
loop. For the output filter, low ESR X5R or X7R
ceramic capacitors are required. Y5V or
equivalent dielectric formulations must not be
used as these lose capacitance with frequency,
temperature and bias voltage.
Recommended Output Capacitors
Description
47uF, 6.3V, 20%
X5R, 1206
(2 capacitorsneeded)
10uF, 6.3V, 10%
X5R, 0805
(Optional 1 capacitor in
parallel with 2x47uF)
MFG
Murata
Taiyo Yuden
Murata
P/N
GRM31CR60J476ME19L
JMK212BJ476ML-T
GRM21BR60J106KE19L
Taiyo Yuden JMK212BJ106KG-T
series inductance, ESL:
EN5394QI
Z = ESR + ESL.
Placing multiple capacitors in parallel reduces
the impedance and hence will result in lower
ripple voltage.
1 = 1 + 1 + ... + 1
ZTotal Z1 Z 2
Zn
Typical ripple versus capacitor arrangement is
given below:
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
(as measured on EN5394QI
Evaluation Board)†
2x47uF
20mV
2x47uF + 1x10uF
12mV
† 20 MHz bandwidth limit
Ternary Pin Inputs
The three ternary pins MAR1, MAR2, and M/S
have three possible states. In the Low state, the
pins are to be tied to GND. In the floating state,
nothing is to be connected to the pins. In the
High state, they are to be tied to VIN through an
external resistor REXT in order to limit the input
current to the pin (see Figure 5). The Electrical
Characteristics table lists, as a function of VIN,
some recommended values for REXT, and the
resulting input currents.
Frequency Sync & Phase Delay
The EN5394 can be synchronized to an external
clock source or to another EN5394 in order to
eliminate unwanted beat frequencies.
Furthermore, two or more synchronized
EN5394’s can have a programmable phase
delay with respect to each other to minimize input
voltage ripple and noise. An example of
synchronizing three EN5394’s with approximately
equal phase delay between them is shown in
Figures 6 and 7. The lowest allowable value for
the S_DELAY resistor is 10kΩ.
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 4MHz switching frequency, the capacitor
impedance, denoted as Z, is comprised mainly of
effective series resistance, ESR, and effective
Power-Up Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
03738
13
October 11, 2013
www.altera.com/enpirion
Rev E
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