EN5394QI Просмотр технического описания (PDF) - Altera Corporation

Номер в каталоге

Компоненты Описание

производитель

EN5394QI

9A PowerSoC Voltage Mode Synchronous Buck PWM DC-DC Converter With Integrated Inductor

Altera Corporation 

be powered when AVIN is off. During power

down, the AVIN should not be powered down

before the PVIN. Tying PVIN and AVIN or all

EN5394QI

three pins (AVIN, PVIN, ENABLE) together

during power up or power down meets these

requirements.

2.5V

Rext

250

VIN

D1

Vf ~ 2V

AGND

R3

3k

IC Package

R1

100k

To Gates

R2

100k

Figure 5: Equivalent circuit of a ternary pin

(MAR1, MAR2, or M/S) input buffer. To get a

logic High on a ternary input, pull the pin to VIN

through an external resistor REXT. See Electrical

Characteristics table for some recommended

REXT values as a function of VIN and the resulting

input currents.

VIN

EXT_CLK

X1

S_IN

VFB

EN5364

S_OUT

VOUT

OUT1

X1_1

S_IN

R4

C1

VFB

EN5364

S_OUT

VOUT

OUT2

X1_2

S_IN

R6

C2

VFB

EN5364

S_OUT

VOUT

R1

GND

R5

R2

R7

R3

Figure 6: Example of synchronizing multiple EN5394QIs in a daisy chain with phase delay.

OUT3

R8

C3

R9

Delay ~ 140°

VDRAIN- 1

VDRAIN- 2

Delay ~ 120°

VDRAIN- 3

Figure 7: Example of a possible way to synchronize and use delays advantageously to minimize input ripple.

R1 ~ 39kΩ , R2 ~ 33kΩ. (Refer to Figure 6 for R1 and R2.) R3 does not matter in this case.

03738

14

October 11, 2013

www.altera.com/enpirion

Rev E

Share Link: