R5F7131 Просмотр технического описания (PDF) - Renesas Electronics
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R5F7131 Datasheet PDF : 1184 Pages
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5.5.3 Illegal Slot Instructions ........................................................................................... 88
5.5.4 General Illegal Instructions..................................................................................... 88
5.6 Cases when Exceptions are Accepted .................................................................................. 89
5.7 Stack States after Exception Handling Ends ........................................................................ 90
5.8 Usage Notes ......................................................................................................................... 92
5.8.1 Value of Stack Pointer (SP) .................................................................................... 92
5.8.2 Value of Vector Base Register (VBR) .................................................................... 92
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling .......... 92
5.8.4 Notes on Slot Illegal Instruction Exception Handling ............................................ 93
Section 6 Interrupt Controller (INTC) .................................................................95
6.1 Features................................................................................................................................ 95
6.2 Input/Output Pins ................................................................................................................. 97
6.3 Register Descriptions ........................................................................................................... 98
6.3.1 Interrupt Control Register 0 (ICR0)........................................................................ 99
6.3.2 IRQ Control Register (IRQCR) ............................................................................ 100
6.3.3 IRQ Status register (IRQSR) ................................................................................ 102
6.3.4 Interrupt Priority Registers A, D to F, and H to M (IPRA, IPRD to IPRF,
and IPRH to IPRM) .............................................................................................. 105
6.4 Interrupt Sources................................................................................................................ 108
6.4.1 External Interrupts ................................................................................................ 108
6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 109
6.4.3 User Break Interrupt (SH7136 and SH7137 only) ................................................ 109
6.5 Interrupt Exception Handling Vector Table....................................................................... 110
6.6 Interrupt Operation............................................................................................................. 114
6.6.1 Interrupt Sequence ................................................................................................ 114
6.6.2 Stack after Interrupt Exception Handling ............................................................. 117
6.7 Interrupt Response Time.................................................................................................... 117
6.8 Data Transfer with Interrupt Request Signals .................................................................... 119
6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation
and CPU Interrupts ............................................................................................... 120
6.8.2 Handling Interrupt Request Signals as Sources for DTC Activation,
but Not CPU Interrupts ......................................................................................... 120
6.8.3 Handling Interrupt Request Signals as Sources for CPU Interrupts,
but Not DTC Activation........................................................................................ 121
6.9 Usage Note......................................................................................................................... 121
Section 7 User Break Controller (UBC) (SH7136 and SH7137 only) ..............123
7.1 Features.............................................................................................................................. 123
7.2 Input/Output Pins ............................................................................................................... 125
Rev. 3.00 Jan. 18, 2010 Page ix of xxiv
REJ09B0402-0300
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