R5F7131 Просмотр технического описания (PDF) - Renesas Electronics
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R5F7131 Datasheet PDF : 1184 Pages
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10.3.22 Timer Output Level Buffer Register (TOLBR) .................................................... 317
10.3.23 Timer Gate Control Register (TGCR) .................................................................. 318
10.3.24 Timer Subcounter (TCNTS) ................................................................................. 320
10.3.25 Timer Dead Time Data Register (TDDR)............................................................. 321
10.3.26 Timer Cycle Data Register (TCDR) ..................................................................... 321
10.3.27 Timer Cycle Buffer Register (TCBR)................................................................... 322
10.3.28 Timer Interrupt Skipping Set Register (TITCR) ................................................... 322
10.3.29 Timer Interrupt Skipping Counter (TITCNT)....................................................... 324
10.3.30 Timer Buffer Transfer Set Register (TBTER) ...................................................... 325
10.3.31 Timer Dead Time Enable Register (TDER).......................................................... 326
10.3.32 Timer Waveform Control Register (TWCR) ........................................................ 327
10.3.33 Bus Master Interface ............................................................................................. 329
10.4 Operation ........................................................................................................................... 330
10.4.1 Basic Functions..................................................................................................... 330
10.4.2 Synchronous Operation......................................................................................... 336
10.4.3 Buffer Operation ................................................................................................... 338
10.4.4 Cascaded Operation .............................................................................................. 342
10.4.5 PWM Modes ......................................................................................................... 347
10.4.6 Phase Counting Mode........................................................................................... 352
10.4.7 Reset-Synchronized PWM Mode.......................................................................... 359
10.4.8 Complementary PWM Mode................................................................................ 362
10.4.9 A/D Converter Start Request Delaying Function.................................................. 406
10.4.10 MTU2–MTU2S Synchronous Operation.............................................................. 410
10.4.11 External Pulse Width Measurement...................................................................... 416
10.4.12 Dead Time Compensation..................................................................................... 417
10.4.13 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 419
10.5 Interrupt Sources................................................................................................................ 420
10.5.1 Interrupt Sources and Priorities............................................................................. 420
10.5.2 DTC Activation..................................................................................................... 422
10.5.3 A/D Converter Activation..................................................................................... 423
10.6 Operation Timing............................................................................................................... 425
10.6.1 Input/Output Timing ............................................................................................. 425
10.6.2 Interrupt Signal Timing......................................................................................... 432
10.7 Usage Notes ....................................................................................................................... 437
10.7.1 Module Standby Mode Setting ............................................................................. 437
10.7.2 Input Clock Restrictions ....................................................................................... 437
10.7.3 Caution on Period Setting ..................................................................................... 438
10.7.4 Contention between TCNT Write and Clear Operations...................................... 438
10.7.5 Contention between TCNT Write and Increment Operations............................... 439
10.7.6 Contention between TGR Write and Compare Match .......................................... 440
Rev. 3.00 Jan. 18, 2010 Page xiii of xxiv
REJ09B0402-0300
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