R5F7131 Просмотр технического описания (PDF) - Renesas Electronics

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R5F7131

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

7.3 Register Descriptions ......................................................................................................... 126

7.3.1 Break Address Register A (BARA) ...................................................................... 127

7.3.2 Break Address Mask Register A (BAMRA)......................................................... 127

7.3.3 Break Bus Cycle Register A (BBRA)................................................................... 128

7.3.4 Break Data Register A (BDRA) ........................................................................... 130

7.3.5 Break Data Mask Register A (BDMRA) .............................................................. 131

7.3.6 Break Address Register B (BARB) ...................................................................... 132

7.3.7 Break Address Mask Register B (BAMRB) ......................................................... 133

7.3.8 Break Data Register B (BDRB) ............................................................................ 134

7.3.9 Break Data Mask Register B (BDMRB)............................................................... 135

7.3.10 Break Bus Cycle Register B (BBRB) ................................................................... 136

7.3.11 Break Control Register (BRCR) ........................................................................... 138

7.3.12 Execution Times Break Register (BETR)............................................................. 143

7.3.13 Branch Source Register (BRSR)........................................................................... 144

7.3.14 Branch Destination Register (BRDR)................................................................... 145

7.4 Operation ........................................................................................................................... 146

7.4.1 Flow of the User Break Operation ........................................................................ 146

7.4.2 User Break on Instruction Fetch Cycle ................................................................. 147

7.4.3 Break on Data Access Cycle................................................................................. 148

7.4.4 Sequential Break ................................................................................................... 149

7.4.5 Value of Saved Program Counter ......................................................................... 149

7.4.6 PC Trace ............................................................................................................... 150

7.4.7 Usage Examples.................................................................................................... 151

7.5 Usage Notes ....................................................................................................................... 156

Section 8 Data Transfer Controller (DTC)........................................................159

8.1 Features.............................................................................................................................. 159

8.2 Register Descriptions ......................................................................................................... 161

8.2.1 DTC Mode Register A (MRA) ............................................................................. 162

8.2.2 DTC Mode Register B (MRB).............................................................................. 163

8.2.3 DTC Source Address Register (SAR)................................................................... 165

8.2.4 DTC Destination Address Register (DAR)........................................................... 165

8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 166

8.2.6 DTC Transfer Count Register B (CRB)................................................................ 167

8.2.7 DTC Enable Registers A to E (DTCERA to DTCERE) ....................................... 168

8.2.8 DTC Control Register (DTCCR) .......................................................................... 169

8.2.9 DTC Vector Base Register (DTCVBR)................................................................ 171

8.2.10 Bus Function Extending Register (BSCEHR) ...................................................... 171

8.3 Activation Sources............................................................................................................. 172

8.4 Location of Transfer Information and DTC Vector Table ................................................. 172

Rev. 3.00 Jan. 18, 2010 Page x of xxiv

REJ09B0402-0300

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