R5F7131 Просмотр технического описания (PDF) - Renesas Electronics

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R5F7131

Renesas 32-Bit RISC Microcomputer SuperH™ RISC engine Family

Renesas Electronics 

8.5 Operation ........................................................................................................................... 177

8.5.1 Transfer Information Read Skip Function ............................................................ 182

8.5.2 Transfer Information Writeback Skip Function .................................................... 183

8.5.3 Normal Transfer Mode ......................................................................................... 183

8.5.4 Repeat Transfer Mode........................................................................................... 184

8.5.5 Block Transfer Mode ............................................................................................ 186

8.5.6 Chain Transfer ...................................................................................................... 187

8.5.7 Operation Timing.................................................................................................. 189

8.5.8 Number of DTC Execution Cycles ....................................................................... 192

8.5.9 DTC Bus Release Timing ..................................................................................... 194

8.5.10 DTC Activation Priority Order ............................................................................. 197

8.6 DTC Activation by Interrupt.............................................................................................. 198

8.7 Examples of Use of the DTC ............................................................................................. 199

8.7.1 Normal Transfer Mode ......................................................................................... 199

8.7.2 Chain Transfer when Counter = 0......................................................................... 199

8.8 Interrupt Sources................................................................................................................ 201

8.9 Usage Notes ....................................................................................................................... 201

8.9.1 Module Standby Mode Setting ............................................................................. 201

8.9.2 On-Chip RAM ...................................................................................................... 201

8.9.3 DTCE Bit Setting.................................................................................................. 201

8.9.4 Chain Transfer ...................................................................................................... 201

8.9.5 Transfer Information Start Address, Source Address, and Destination

Address ................................................................................................................. 201

8.9.6 Access to DTC Registers through DTC ................................................................ 202

8.9.7 Notes on IRQ Interrupt as DTC Activation Source .............................................. 202

8.9.8 Notes on SCI as DTC Activation Sources ............................................................ 202

8.9.9 Clearing Interrupt Source Flag.............................................................................. 202

8.9.10 Conflict between NMI Interrupt and DTC Activation .......................................... 202

8.9.11 Operation When a DTC Activation Request is Cancelled While in Progress....... 202

Section 9 Bus State Controller (BSC)................................................................203

9.1 Features.............................................................................................................................. 203

9.2 Input/Output Pins ............................................................................................................... 205

9.3 Area Overview ................................................................................................................... 205

9.3.1 Area Division........................................................................................................ 205

9.3.2 Address Map ......................................................................................................... 205

9.4 Register Descriptions ......................................................................................................... 211

9.4.1 Common Control Register (CMNCR) .................................................................. 211

9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 and 1)................................... 213

9.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 and 1)................................ 216

Rev. 3.00 Jan. 18, 2010 Page xi of xxiv

REJ09B0402-0300

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