R5F7131 Просмотр технического описания (PDF) - Renesas Electronics
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R5F7131 Datasheet PDF : 1184 Pages
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9.4.4 Bus Function Extending Register (BSCEHR) ...................................................... 218
9.5 Operation ........................................................................................................................... 222
9.5.1 Endian/Access Size and Data Alignment.............................................................. 222
9.5.2 Normal Space Interface ........................................................................................ 223
9.5.3 Access Wait Control ............................................................................................. 226
9.5.4 CSn Assert Period Extension ................................................................................ 228
9.5.5 Wait between Access Cycles ................................................................................ 229
9.5.6 Bus Arbitration ..................................................................................................... 232
9.5.7 Others.................................................................................................................... 236
9.5.8 Access to On-Chip FLASH and On-Chip RAM by CPU ..................................... 237
9.5.9 Access to On-Chip Peripheral I/O Registers by CPU ........................................... 237
9.5.10 Access to External Memory by CPU .................................................................... 239
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)...................................241
10.1 Features.............................................................................................................................. 241
10.2 Input/Output Pins............................................................................................................... 247
10.3 Register Descriptions ......................................................................................................... 248
10.3.1 Timer Control Register (TCR).............................................................................. 252
10.3.2 Timer Mode Register (TMDR)............................................................................. 256
10.3.3 Timer I/O Control Register (TIOR) ...................................................................... 259
10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR) .................................... 278
10.3.5 Timer Interrupt Enable Register (TIER)............................................................... 279
10.3.6 Timer Status Register (TSR)................................................................................. 284
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 292
10.3.8 Timer Input Capture Control Register (TICCR) ................................................... 293
10.3.9 Timer Synchronous Clear Register (TSYCR)....................................................... 295
10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 297
10.3.11 Timer A/D Converter Start Request Cycle Set Registers
(TADCORA_4 and TADCORB_4)...................................................................... 300
10.3.12 Timer A/D Converter Start Request Cycle Set Buffer Registers
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 300
10.3.13 Timer Counter (TCNT)......................................................................................... 301
10.3.14 Timer General Register (TGR) ............................................................................. 301
10.3.15 Timer Start Register (TSTR) ................................................................................ 302
10.3.16 Timer Synchronous Register (TSYR)................................................................... 304
10.3.17 Timer Counter Synchronous Start Register (TCSYSTR) ..................................... 306
10.3.18 Timer Read/Write Enable Register (TRWER) ..................................................... 309
10.3.19 Timer Output Master Enable Register (TOER) .................................................... 310
10.3.20 Timer Output Control Register 1 (TOCR1) .......................................................... 311
10.3.21 Timer Output Control Register 2 (TOCR2) .......................................................... 314
Rev. 3.00 Jan. 18, 2010 Page xii of xxiv
REJ09B0402-0300
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