ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
the Analog Devices website (www.analog.com)—use site search
on “EE-68.” This document is updated regularly to keep pace
with improvements to emulator support.
Additional Information
This data sheet provides a general overview of the ADSP-TS101S
processor’s architecture and functionality. For detailed informa-
tion on the ADSP-TS101S processor’s core architecture and
instruction set, see the ADSP-TS101 TigerSHARC Processor Pro-
gramming Reference and the ADSP-TS101 TigerSHARC Processor
Hardware Reference. For detailed information on the development
tools for this processor, see the VisualDSP++ User’s Guide for
TigerSHARC Processors.
PIN FUNCTION DESCRIPTIONS
While most of the ADSP-TS101S processor’s input pins are
normally synchronous—tied to a specific clock—a few are asyn-
chronous. For these asynchronous signals, an on-chip
synchronization circuit prevents metastability problems. The
synchronous ac specification for asynchronous signals is used
only when predictable cycle-by-cycle behavior is required.
All inputs are sampled by a clock reference, therefore input spec-
ifications (asynchronous minimum pulsewidths or synchronous
input setup and hold) must be met to guarantee recognition.
Pin States at Reset
The output pins can be three-stated during normal operation.
The DSP three-states all outputs during reset, allowing these pins
to get to their internal pull-up or pull-down state. Some output
pins (control signals) have a pull-up or pull-down that maintains
a known value during transitions between different drivers.
Pin Definitions
The Type column in the following pin definitions tables describes
the pin type, when the pin is used in the system. The Term (for
termination) column describes the pin termination type if the pin
is not used by the system. Note that some pins are always used
(indicated with au symbol).
Table 3. Pin Definitions—Clocks and Reset
Signal
Type
Term Description
LCLK_N
I
LCLK_P
I
LCLKRAT2–01
I (pd2)
SCLK_N
I
SCLK_P
I
SCLKFREQ3
RESET
I (pu2)
I/A
au Local Clock Reference. Connect this pin to VREF as shown in Figure 5.
au Local Clock Input. DSP clock input. The instruction cycle rate = n × LCLK,
where n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6. See Clock Domains
on Page 9.
au LCLK Ratio. The DSP’s core clock (instruction cycle rate) = n × LCLK, where
n is user-programmable to 2, 2.5, 3, 3.5, 4, 5, or 6 as shown in Table 4. These
pins must have a constant value while the DSP is powered.
au System Clock Reference. Connect this pin to VREF as shown in Figure 5.
au System Clock Input. The DSP’s system input clock for cluster bus. This pin
must be connected to the same clock source as LCLK_P. See Clock Domains
on Page 9.
au SCLK Frequency. SCLKFREQ = 1 is required. The SCLKFREQ pin must
have a constant value while the DSP is powered.
au Reset. Sets the DSP to a known state and causes program to be in idle state.
RESET must be asserted at specified time according to the type of reset
operation. For details, see Reset and Booting on Page 8.
Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;
pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state
Term (for termination) column symbols: epd = External pull-down approximately 10 kΩ to VSS; epu = External pull-up approximately 10 kΩ to VDD-IO
nc = Not connected; au = Always used.
1 The internal pull-down may not be sufficient. A stronger pull-down may be necessary.
2 See ELECTRICAL CHARACTERISTICS on Page 19 for maximum and minimum current consumption for pull-up and pull-down resistances.
3 The internal pull-up may not be sufficient. A stronger pull-up may be necessary.
Table 4. LCLK Ratio
LCLKRAT2–0
000 (default)
001
010
011
100
Ratio
2
2.5
3
3.5
4
Table 4. LCLK Ratio (continued)
LCLKRAT2–0
101
110
111
Ratio
5
6
Reserved
REV. A
–11–
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