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ADSP-TS101S
(Rev.:RevA)

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

Table 5. Pin Definitions—External Port Bus Controls

Signal

Type

Term Description

ADDR31–01

I/O/T

nc Address Bus. The DSP issues addresses for accessing memory and peripherals

on these pins. In a multiprocessor system, the bus master drives addresses for

accessing internal memory or I/O processor registers of other ADSP-TS101S

processors. The DSP inputs addresses when a host or another DSP accesses

its internal memory or I/O processor registers.

DATA63–01

I/O/T

nc External Data Bus. Data and instructions are received, and driven by the DSP,

on these pins.

RD2

I/O/T

nc Memory Read. RD is asserted whenever the DSP reads from any slave in the

(pu3)

system, excluding SDRAM. When the DSP is a slave, RD is an input and

indicates read transactions that access its internal memory or universal

registers. In a multiprocessor system, the bus master drives RD. The RD pin

changes concurrently with ADDR pins.

WRL2

I/O/T

(pu3)

nc Write Low. WRL is asserted in two cases: When the ADSP-TS101S writes to

an even address word of external memory or to another external bus agent;

and when the ADSP-TS101S writes to a 32-bit zone (host, memory, or DSP

programmed to 32-bit bus). An external master (host or DSP) asserts WRL

for writing to a DSP’s low word of internal memory. In a multiprocessor

system, the bus master drives WRL. The WRL pin changes concurrently with

ADDR pins. When the DSP is a slave, WRL is an input and indicates write

transactions that access its internal memory or universal registers.

WRH2

I/O/T

nc Write High. WRH is asserted when the ADSP-TS101S writes a long word

(pu3)

(64 bits) or writes to an odd address word of external memory or to another

external bus agent on a 64-bit data bus. An external master (host or another

DSP) must assert WRH for writing to a DSP’s high word of 64-bit data bus.

In a multiprocessing system, the bus master drives WRH. The WRH pin

changes concurrently with ADDR pins. When the DSP is a slave, WRH is an

input and indicates write transactions that access its internal memory or

universal registers.

ACK

I/O/T

epu Acknowledge. External slave devices can deassert ACK to add wait states to

external memory accesses. ACK is used by I/O devices, memory controllers,

and other peripherals on the data phase. The DSP can deassert ACK to add

wait states to read accesses of its internal memory. The ADSP-TS101S does

not drive ACK during slave writes. Therefore, an external (approximately

BMS2, 4

O/T

au

(pu/pd3)

10 kΩ) pull-up is required.

Boot Memory Select. BMS is the chip select for boot EPROM or flash

memory. During reset, the DSP uses BMS as a strap pin (EBOOT) for

EPROM boot mode. When the DSP is configured to boot from EPROM,

BMS is active during the boot sequence. Pull-down enabled during RESET

(asserted); pull-up enabled after RESET (deasserted). In a multiprocessor

system, the DSP bus master drives BMS. For details see Reset and Booting

on Page 8 and the EBOOT signal description in Table 16 on Page 18.

Type column symbols: A = Asynchronous; G = Ground; I = Input; O = Output; o/d = Open drain output; P = Power supply;

pd = Internal pull-down approximately 100 kΩ; pu = Internal pull-up approximately 100 kΩ; T = Three-state

Term (for termination) column symbols: epd = External pull-down approximately 10 kΩ to VSS; epu = External pull-up approximately 10 kΩ to VDD-IO

nc = Not connected; au = Always used.

–12–

REV. A

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