FXAS21002CQR1 Просмотр технического описания (PDF) - NXP Semiconductors.

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производитель

FXAS21002CQR1

3-Axis Digital Angular Rate Gyroscope

NXP Semiconductors. 

Digital Interfaces

3.2.3 SPI Read Operations with 4-Wire Mode

NOTE

This description pertains only to the default SPI 4-wire

interface mode (with CTRL_REG0[SPIW] = 0). This mode is

the default out of POR, or after a hard/soft reset.

A register read operation is initiated by transmitting a 1 for the R/W bit. Then, the 7-bit

register read address, A[6:0] is encoded in the first byte. The data is read from the

MISO pin (MSB first). Figure 12 shows the bus protocol for a single byte read

operation.

SPI_CS_B

SCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MOSI

R/W A6 A5 A4 A3 A2 A1 A0

MISO

D7 D6 D5 D4 D3 D2 D1 D0

Figure 12. SPI single byte read protocol diagram (4-wire mode), R/W = 1

Multiple-byte read operations are performed similarly to single-byte reads; additional

bytes are read in multiples of eight SCLK cycles. The register read address is auto-

incremented by FXAS21002C so that every eighth clock edge will latch the address of

the next register read address. When the desired number of bytes has been read, the

rising edge on the SPI_CS_B terminates the transaction.

SPI_CS_B

SCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MOSI

R/W A6 A5 A4 A3 A2 A1 A0

MISO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 13. SPI multiple byte read protocol diagram (4-wire mode), R/W = 1

20

Freescale Semiconductor, Inc.

3-Axis Digital Angular Rate Gyroscope, Rev. 2.1, 5/2015

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