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FXAS21002CQR1 Просмотр технического описания (PDF) - NXP Semiconductors.

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Компоненты Описание
производитель
FXAS21002CQR1
NXP
NXP Semiconductors. NXP
FXAS21002CQR1 Datasheet PDF : 58 Pages
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Digital Interfaces
3.1.3.3 I²C Data Sequence Diagrams
<Single Byte Read>
Master
ST Device Address[6:0] W
Register Address[7:0]
SR Device Address[6:0] R
NACK SP
Slave
ACK
ACK
ACK Data[7:0]
<Multiple Byte Read>
Master
Slave
ST Device Address[6:0] W
Register Address[7:0]
SR Device Address[6:0] R
ACK
ACK
ACK
ACK
continued
Data[7:0]
Master
ACK
ACK
NACK SP
Slave Data[7:0]
Data[7:0]
Data[7:0]
<Single Byte Write>
Master
ST Device Address[6:0] W
Register Address[7:0]
Data[7:0]
SP
Slave
ACK
ACK
ACK
<Multiple Byte Write>
Master
ST Device Address[6:0] W
Register Address[7:0]
Data[7:0]
Data[7:0]
SP
Slave
Legend
ST: Start Condition
ACK
ACK
ACK
SP: Stop Condition ACK: Acknowledge NACK: No Acknowledge
W: Write = 0
Figure 7. I²C data sequence diagram
ACK
SR: Repeated Start Condition
3.2 SPI Interface
The SPI interface is a classical Master/Slave serial port. FXAS21002C is always
considered to be the slave device and thus never initiates a communication with the
host processor.
The SPI interface of FXAS21002C is compatible with SPI interface mode 00,
corresponding to CPOL = 0 and CPHA = 0.
For CPOL = 0, the idle value of the clock is zero, and the active value of the clock is
1. For CPHA = 0, data is captured on the clock's rising edge (low to high transition)
and data is propagated on the clock’s falling edge (high to low transition).
3-Axis Digital Angular Rate Gyroscope, Rev. 2.1, 5/2015
17
Freescale Semiconductor, Inc.

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