FXAS21002CQR1 Просмотр технического описания (PDF) - NXP Semiconductors.

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Компоненты Описание

производитель

FXAS21002CQR1

3-Axis Digital Angular Rate Gyroscope

NXP Semiconductors. 

Digital Interfaces

SPI_CS_B

SCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

MOSI

MISO

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

Figure 9. SPI single byte write protocol diagram (3-wire mode), R/W = 0

Multiple-byte write operations are performed similarly to the single-byte write

sequence, but with additional data bytes transferred over every 8 SCLK cycle period.

The register write address is internally auto-incremented by FXAS21002C so that

every eighth clock edge will latch the address for the next register write address.

When the desired number of bytes has been written, the rising edge on the SPI_CS_B

pin terminates the transaction. Figure 10 and Figure 11 show the bus protocol for

multiple byte register write operation in either 3- or 4-wire SPI modes.

SPI_CS_B

SCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MOSI

MISO

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

Figure 10. SPI multiple byte write protocol diagram (4-wire mode), R/W = 0

SPI_CS_B

SCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MOSI

MISO

R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

High-Impedance

Figure 11. SPI multiple byte write protocol diagram (3-wire mode), R/W = 0

3-Axis Digital Angular Rate Gyroscope, Rev. 2.1, 5/2015

19

Freescale Semiconductor, Inc.

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