FXAS21002CQR1 Просмотр технического описания (PDF) - NXP Semiconductors.

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FXAS21002CQR1

3-Axis Digital Angular Rate Gyroscope

NXP Semiconductors. 

Digital Interfaces

tr

SDA

70%

30%

SCL

tSET

S

tr

tSU:DAT

70%

30%

tr

tHD :DAT

70%

30%

1st

1 / fSCL

clock cycle

70%

30%

tr

70%

30%

tLOW

tHIGH

tVD:DAT

70%

30%

SDA

tSU:STA

SCL

tBUF

tHD:STA

tSP

tVD:ACK

tSU:STO

70%

Sr

30%

P

S

9th clock

Figure 6. I2C timing diagram

9th clock

3.1.1 I²C Operation

There are two signals associated with the I2C bus: the serial clock line (SCL) and the

serial data line (SDA). The SDA is a bidirectional line used for sending and receiving

the data to and from the interface. External pull-up resistors connected to VDDIO are

required for SDA and SCL. When the bus is free, the lines are high.

The maximum practical operating frequency for I2C in a given system implementation

depends on several factors including the pull-up resistor values, and the total bus

capacitance (trace + parasitic device capacitances).

A transaction on the bus is started through a start condition (ST) signal, which is

defined as a HIGH-to-LOW transition on the data line while the SCL line is held HIGH.

After the ST signal has been transmitted by the master, the bus is considered busy. The

next byte of data transmitted contains the slave address in the first seven bits, and the

eighth bit, the read/write bit, indicates whether the master is receiving data from the

slave or transmitting data to the slave. When an address is sent, each device in the

system compares the first seven bits after the ST condition with its own address. If they

match, the device considers itself addressed by the master. The ninth clock pulse,

following the slave address byte (and each subsequent byte) is the acknowledge (ACK).

14

Freescale Semiconductor, Inc.

3-Axis Digital Angular Rate Gyroscope, Rev. 2.1, 5/2015

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