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T8302

Internet Protocol Telephone Advanced RISC Machine (ARM®) Ethernet QoS Using IEEE® 802.1q

Agere -> LSI Corporation 

Data Sheet

July 2001

T8302 Internet Protocol Telephone

Advanced RISC Machine (ARM )

Table of Contents (continued)

Contents

Page

19.3.1 System Clock Crystal .................................................................................................................. 242

19.4 PHY Clock Crystal .................................................................................................................................. 243

19.5 Real-Time Clock Crystal ........................................................................................................................ 243

19.6 dc Electrical Characteristics ...................................................................................................................243

19.7 Power Consumption ...............................................................................................................................244

20 Change History .............................................................................................................................................. 245

21 Contact Us ...................................................................................................................................................... 245

Figures

Page

Figure 1. 272-Pin PBGA Pin Diagram .....................................................................................................................17

Figure 2. IPT_ARM Block Diagram ......................................................................................................................... 27

Figure 3. Reset/Clock Management Controller Block Diagram ...............................................................................29

Figure 4. Real-Time Clock Block Diagram ..............................................................................................................34

Figure 5. Interrupt Controller Block Diagram ........................................................................................................... 48

Figure 6. DMA Controller Block Diagram 1 ............................................................................................................. 56

Figure 7. DMA Controller Block Diagram 2 ............................................................................................................. 60

Figure 8. Programmable Timer Architecture Block Diagram ................................................................................... 70

Figure 9. Interval Timer Block Diagram ................................................................................................................... 71

Figure 10. Watchdog Timer Block Diagram............................................................................................................. 72

Figure 11. EMI FLASH/SRAM Read Interface Timing Diagram .............................................................................. 81

Figure 12. EMI FLASH/SRAM Write Interface Timing Diagram .............................................................................. 82

Figure 13. ROM/RAM Remapping........................................................................................................................... 83

Figure 14. SDRAM Read Timing Diagram ..............................................................................................................92

Figure 15. SDRAM Write Timing Diagram............................................................................................................... 93

Figure 16. DSP Communications Controller Block Diagram ................................................................................... 96

Figure 17. DSP Read Interface Timing Diagram ..................................................................................................... 99

Figure 18. DSP Write Interface Timing Diagram ................................................................................................... 100

Figure 19. Ethernet 10/100 MAC Block Diagram .................................................................................................. 101

Figure 20. Repeater Slice and Backplane Segment Block ....................................................................................123

Figure 21. USB Block Diagram.............................................................................................................................. 162

Figure 22. ACC Block Diagram ............................................................................................................................. 187

Figure 23. IrDA Transmit Data Timing Diagram and Width Programmability ........................................................198

Figure 24. IrDA Receive Data Timing Diagram, Minimum Pulse Width ................................................................ 199

Figure 25. SSI Functional Block Diagram.............................................................................................................. 202

Figure 26. SSI Transfer Timing Diagram, (SPHA = 0)........................................................................................... 208

Figure 27. SSI Transfer Timing Diagram, (SPHA = 1)........................................................................................... 210

Figure 28. Parallel Peripheral Interface (PPI) Block Diagram ............................................................................... 215

Figure 29. Minimum Data Input Pulse Width ......................................................................................................... 217

Figure 30. KLC Interface Matrix............................................................................................................................. 223

Figure 31. Boundary Scan Architecture................................................................................................................. 232

Figure 32. JTAG Interface Timing Diagram........................................................................................................... 233

Agere Systems Inc.

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