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T8302

Internet Protocol Telephone Advanced RISC Machine (ARM®) Ethernet QoS Using IEEE® 802.1q

Agere -> LSI Corporation 

T8302 Internet Protocol Telephone

Advanced RISC Machine (ARM )

Data Sheet

July 2001

2 Pinout Information (continued)

2.2 Pin List

Table 1. PBGA-272 Package

Ball Signal

Description

I/O Pull-Up/Down Source/Sink

Current

ARM to DSP Communications Interface

H1 DSP_A[0] DSP interface address bus bit 0 (LSB)

I

—

7 ma/7 ma

J4 DSP_A[1] DSP interface address bus bit 1

I

—

7 ma/7 ma

J3 DSP_A[2] DSP interface address bus bit 2

I

—

7 ma/7 ma

J2 DSP_A[3] DSP interface address bus bit 3

I

—

7 ma/7 ma

J1 DSP_A[4] DSP interface address bus bit 4

I

—

7 ma/7 ma

K2 DSP_A[5] DSP interface address bus bit 5

I

—

7 ma/7 ma

K3 DSP_A[6] DSP interface address bus bit 6

I

—

7 ma/7 ma

K1 DSP_A[7] DSP interface address bus bit 7

I

—

7 ma/7 ma

L1 DSP_A[8] DSP interface address bus bit 8

I

—

7 ma/7 ma

L2 DSP_A[9] DSP interface address bus bit 9

I

—

7 ma/7 ma

L3 DSP_A[10] DSP interface address bus bit 10 (MSB)

I

—

7 ma/7 ma

B1 DSP_D[0] DSP interface data bus bit 0 (LSB)

I/O 50 kΩ pull-up 7 ma/7 ma

C2 DSP_D[1] DSP interface data bus bit 1

I/O 50 kΩ pull-up 7 ma/7 ma

D2 DSP_D[2] DSP interface data bus bit 2

I/O 50 kΩ pull-up 7 ma/7 ma

D3 DSP_D[3] DSP interface data bus bit 3

I/O 50 kΩ pull-up 7 ma/7 ma

E4 DSP_D[4] DSP interface data bus bit 4

I/O 50 kΩ pull-up 7 ma/7 ma

C1 DSP_D[5] DSP interface data bus bit 5

I/O 50 kΩ pull-up 7 ma/7 ma

D1 DSP_D[6] DSP interface data bus bit 6

I/O 50 kΩ pull-up 7 ma/7 ma

E3 DSP_D[7] DSP interface data bus bit 7

I/O 50 kΩ pull-up 7 ma/7 ma

E2 DSP_D[8] DSP interface data bus bit 8

I/O 50 kΩ pull-up 7 ma/7 ma

E1 DSP_D[9] DSP interface data bus bit 9

I/O 50 kΩ pull-up 7 ma/7 ma

F3 DSP_D[10] DSP interface data bus bit 10

I/O 50 kΩ pull-up 7 ma/7 ma

G4 DSP_D[11] DSP interface data bus bit 11

I/O 50 kΩ pull-up 7 ma/7 ma

F2 DSP_D[12] DSP interface data bus bit 12

I/O 50 kΩ pull-up 7 ma/7 ma

F1 DSP_D[13] DSP interface data bus bit 13

I/O 50 kΩ pull-up 7 ma/7 ma

G3 DSP_D[14] DSP interface data bus bit 14

I/O 50 kΩ pull-up 7 ma/7 ma

G2 DSP_D[15] DSP interface data bus bit 15 (MSB)

I/O 50 kΩ pull-up 7 ma/7 ma

G1 DSP_RWN Read high write low memory signal

I

—

7 ma/7 ma

H3 DSP_MCSN Chip select interprocessor memory

I

—

7 ma/7 ma

H2 DSP_ICSN Chip select interprocessor semaphores and interrupt I/O

—

7 ma/7 ma

L4 DSP_INTN0 DSP interrupt

I/O

—

7 ma/7 ma

Crystal for Main Clock and Real-Time Clock

P4

XRTC0 Input pin to connect 32.768 kHz crystal

I

—

—

T1

XRTC1 Output pin to connect 32.768 kHz crystal

O

—

—

T4

XTAL0 Output pin to connect 11.52 MHz crystal

O

—

—

V1

XTAL1 Input pin to connect 11.52 MHz crystal

I

—

—

M1 TSTCLK Test mode clock input

O

—

4 ma/4 ma

N2

RTS0N Reset output

O

—

4 ma/4 ma

18

Agere Systems Inc.

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