T8302 Просмотр технического описания (PDF) - Agere -> LSI Corporation

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T8302

Internet Protocol Telephone Advanced RISC Machine (ARM®) Ethernet QoS Using IEEE® 802.1q

Agere -> LSI Corporation 

T8302 Internet Protocol Telephone

Advanced RISC Machine (ARM )

Data Sheet

July 2001

Table of Contents

Tables

Page

Table 1. PBGA-272 Package ................................................................................................................................. 18

Table 2. ARM Processor Memory and I/O Map ...................................................................................................... 28

Table 3. Reset/Clock Management Controller Signals ........................................................................................... 30

Table 4. Reset/Clock Controller Register Map ....................................................................................................... 35

Table 5. Pause Register ......................................................................................................................................... 36

Table 6. Version ID Register 0xE000 0010 ............................................................................................................ 36

Table 7. Clock Management Register ..................................................................................................................... 37

Table 8. Clock Status Register ................................................................................................................................ 37

Table 9. System Clock Source Encoding ...............................................................................................................38

Table 10. Clock Control Register ............................................................................................................................ 38

Table 11. Soft Reset Register ................................................................................................................................ 39

Table 12. PLL Control Register .............................................................................................................................. 39

Table 13. Reset Status (Control/Clear) Registers .................................................................................................. 40

Table 14. Reset Peripheral Control (Read, Clear, Set) Registers .......................................................................... 41

Table 15. RTC External Divider Register ...............................................................................................................42

Table 16. RTC Clock Prescale Registers ...............................................................................................................42

Table 17. RTC Control Register ............................................................................................................................. 43

Table 18. RTC Seconds Alarm Register ................................................................................................................ 44

Table 19. RTC Seconds Count Register ................................................................................................................ 44

Table 20. RTC Divider Register .............................................................................................................................. 45

Table 21. RTC Interrupt Status Register ................................................................................................................ 45

Table 22. RTC Interrupt Enable Register ...............................................................................................................45

Table 23. Interrupt Registers ..................................................................................................................................48

Table 24. Interrupt Request Signals (IRQ) ............................................................................................................. 49

Table 25. Programmable Interrupt Controller Register Map ................................................................................... 50

Table 26. Interrupt Request Status Register IRSR .................................................................................................51

Table 27. Interrupt Request Enable Registers IRER (Set = IRESR, Clear = IRECR) ............................................ 51

Table 28. Interrupt Request Soft Register IRQSR .................................................................................................. 52

Table 29. Interrupt Priority Control Registers IPCR[15:1] ....................................................................................... 52

Table 30. Interrupt In-Service Registers ISR (ISRI, ISRF) .....................................................................................53

Table 31. Interrupt Source Encoding for Interrupt In-Service Registers ................................................................. 53

Table 32. Interrupt Request Source Clear Register IRQESCR ..............................................................................54

Table 33. Interrupt Priority Enable Registers IPER (Set = IPESR, Clear = IPECR) ...............................................54

Table 34. External Interrupt Control Registers ....................................................................................................... 55

Table 35. DMA Controller Register Map ................................................................................................................. 61

Table 36. DMA Control Registers for Channels [0:3] ............................................................................................. 62

Table 37. DMA Source Address Registers for Channels [0:3] ............................................................................... 64

Table 38. DMA Preload Destination Start Address Registers for DMA Channels [0:3] .......................................... 64

Table 39. DMA Destination Address Registers for DMA Channels [0:3] ................................................................ 64

Table 40. DMA Preload Transfer Count Registers for Channels [0:3] .................................................................... 65

Table 41. DMA Transfer Count Registers for Channels [0:3] ................................................................................. 65

Table 42. DMA Burst and Hold Count Registers for Channel [0:3] ........................................................................ 66

Table 43. DMA Status Register .............................................................................................................................. 66

Table 44. DMA Interrupt Register ...........................................................................................................................68

Table 45. DMA Interrupt Enable Register ...............................................................................................................69

Table 46. Timer Controller Register Map ...............................................................................................................73

Table 47. Count Rate Register ............................................................................................................................... 74

Table 48. Encoding of Interval Timer and Watchdog Timer Count Rates .............................................................. 74

Table 49. WT Count Register ................................................................................................................................. 75

Table 50. Timer Status Register ............................................................................................................................. 75

10

Agere Systems Inc.

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