TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ9303 Datasheet PDF : 25 Pages
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TQ9303
The Clock Generator generates CRXCLK, a word clock,
which is used for clocking the host I/O registers. The
user may place the clock edge, CRXCLK, in four places
relative to the word input, thereby giving the user
control of setup and hold times. Clock edge placement
is selected via control pins RXCKPH0 and RXCKPH1
(Receiver ClocK PHase). CRXCLK runs at 26.5625␣ MHz
using FC1063 and 13.28125␣ MHz using FC531.
Figure 6. Pinout
The Clock Generator also receives the BRXSYNC signal,
which is used for byte alignment. The Receiver drives
BRXSYNC high when detecting a K28.5 character.
Raw Mode Receive
In Raw Mode Receive where RXRAW is high for the
whole frame, the input data word bypasses the parity
check, ordered set generator, 32-bit CRC, and 8b/10b
encoder, and is directly converted to data words. The
byte-to-word mapping of data is listed in Table␣ 1.
CTXD0
VSS1
BTXD0
BTXD1
BTXD2
VSS1
BTXD3
BTXD4
VDD
BTXD5
BTXD6
VSS1
BTXD7
BTXD8
BTXD9
VSS1
BTXCKIN
VSS1
BTXCKOUT
VDD
BRXCLK
VSS3
BRXD0
BRXD1
BRXD2
BRXD3
VDD3
BRXD4
BRXD5
BRXD6
BRXD7
VSS3
BRXD8
BRXD9
BRXSYNC
VDD
CRXD0
CRXD1
VSS1
CRXD2
1
2
3
4
5
Pin 1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TQ9303
120
CTXC0
119
CTXC1
118
CTXRAWA
117
CTXRAWB
116
CTXCERR
115
CTXPERR
114
TXPENN
113
PL_IDLE
112
CTXCLK
111
TSTMODE
110
CTXWREF
109
VSS1
108
TXPMODE
107
TXRAW
106
RXRAW
105
VSS3
104
RXPMODE
103
VSS2
102
RXCKPH1
101
RXCKPH0
100
VDD3
99
RESETN
98
VSS1
97
CRXCLK
96
VSS1
95
WRDSYNCN
94
RXERROR
93
CRXS5
92
CRXS4
91
VSS1
90
CRXS3
89
CRXS2
88
CRXS1
87
VDD
86
CRXS0
85
CRXP3
84
CRXD31
83
VSS1
82
CRXD30
81
CRXD29
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