TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor
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TQ9303 Datasheet PDF : 25 Pages
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TQ9303
Table 5. Pin Descriptions (continued)
Symbol
CRXD0..31
I/O # of I/O
O
32
CRXS0
O
1
CRXS1
O
1
CRXS2,3
O
2
CRXS4,5
O
2
CRXP0
O
1
CRXP1
O
1
CRXP2
O
1
CRXP3
O
1
RXERROR O
1
RXRAW
I
1
WRDSYNCN O
1
RXPMODE
I
1
RXCKPH0,1 I
2
RESETN
I
1
VDD
—
—
GND (VSS)
—
—
Interface
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
Host
—
—
Description
Receive data output (CRXD31 = MSB; CRXD0 = LSB).
High indicates CRXD0..31 is an Ordered Set;
Low indicates data.
CRC error flag; high indicates a CRC error.
Line state status bits. State equivalent for CRXS3
and CRXS2 from left to right, respectively:
␣ ␣ ␣ ␣ 00 - No State 01 - Pending
␣ ␣ ␣ ␣ 10 - State Rec. 11 - Bad Seq.
Line state ID bits.
CRXD0..7 Odd Parity output.
CRXD8..15 Odd Parity output.
CRXD16..23 Odd Parity output.
CRXD24..31 and optional CRXS01 Odd Parity output.
If RXPMODE is high, CRXP3 generates Parity for
CRXD24..31 and CRXS0. If RXPMODE is low,
CRXP3 generates Parity for CRXD24..31 only.
Receive Error; high indicates invalid data from the Receiver.
High selects Raw Receive Data mode.
Word Synchronization Status Flag;
Low indicates Synchronization aqcuired.
Can be connected to SYNCEN on TQ9502/GA9102 Receiver.
Receiver Parity mode. If RXPMODE is high, CRXP3
generates Parity for CRXD24..31 and CRXS0.
If RXPMODE is low, CRXP3 generates Parity for
CRXD24..31 only.
CRXCLK Phase Select pin.
Active low.
+5 Volt supply.
Ground.
Pin Numbers
37,38,40,41,43,44,
46,47,49,51–53,55,
56,58,59,62,64–66,
68,69,71,72,74,
76,77,79–82,84
86
88
89,90
92,93
48
61
73
85
94
106
95
104
101,102
99
9,20,27,36,42,54,67,
78,87,100,140,154
2,6,12,16,18,22,32,39,
45,50,57,60,63,70,75,
83,91,96,98,103,105,
109,130,134,150
14
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