TQ9303 Просмотр технического описания (PDF) - TriQuint Semiconductor

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производитель

TQ9303

Fibre Channel Encoder/Decoder

TriQuint Semiconductor 

TQ9303

Table 5. Pin Descriptions

Symbol

BTXCKIN

BTXCKOUT

BTXD0..9

CTXWREF

I/O # of I/O

I

1

O

1

O

10

O

1

CTXCLK

I

1

CTXC0

I

1

CTXC1

I

1

CTXD0..31

I

32

CTXP0

CTXP1

CTXP2

CTXP3

I

1

I

1

I

1

I

1

CTXRAWA

I

1

CTXRAWB

I

1

CTXPERR

O

1

CTXCERR

O

1

TSTMODE

I

1

TXRAW

I

1

TXPENN

I

1

TXPMODE

I

1

PL_IDLE

I

1

BRXCLK

I

1

BRXD0..9

I

10

BRXSYNC

I

1

CRXCLK

O

1

Interface

Transmitter

Transmitter

Transmitter

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Host

Receiver

Receiver

Receiver

Host

Description

Takes clock from Transmitter to generate BTXCKOUT.

Used by Transmitter to clock in BTXD0..9.

Data Output.

Reference Word Clock which can be used in signaling the

host to issue a CTXCLK.

Word Clock generated from CTXCLK to clock in/out host I/O

registers. The following signals are latched by CTXCLK:

CTXP0..3, CTXC0,1, CTXRAW, CTXPENN, CTXPMODE,

CTXPERR, CTXCERR.

High indicates CTXD0..31 is an Ordered Set;

Low indicates data.

High generates CRC; low checks CRC.

Transmit data output (CTXD31 = MSB; CTXD0 = LSB).

CTXD0..7 Odd Parity input.

CTXD8..15 Odd Parity input.

CTXD16..23 Odd Parity input.

CTXD24..31 and optional CTXC0 Odd Parity input.

If TXPMODE is high, CTXP3 checks parity for

CTXD24..31 and CTXC0. If TXPMODE is low,

CTXP3 checks parity for CTXD24..31 only.

Raw data bit 19.

Raw data bit 9.

CTXPERR high indicates CTXD0..31 Parity Error.

CTXCERR high indicates CRC Error.

When in CRC Check mode, CTXC1 is low.

Normally GND. HIGH state used by vendor to monitor

delay and threshold.

High selects Raw Transmit Data mode.

Active Low Transmit Parity Enable; Tx checks Parity

when low.

If TXPMODE is high, CTXP3 generates parity for

CTXD24..31 and CTXC0. If TXPMODE is low,

CTXP3 generates parity for CTXD24..31 only.

Proprietary link idle control

Driven by RXCLK. Clocks data from BRXD0..9.

Receives RXD0..9 from Receiver.

SYNC.

CRXCLK latches CRXDO..31.

Pin Numbers

17

19

3–5, 7, 8, 10, 11, 13–15

110

112

120

119

1, 160–155, 153-151,

149–143, 141, 139–135,

133, 132, 129–122

152

142

131

121

118

117

115

116

111

107

114

108

113

21

23–26, 28–31, 33, 34

35

97

(Continued on next page)

For additional information and latest specifications, see our website: www.triquint.com

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