CXD1186CQ Просмотр технического описания (PDF) - Sony Semiconductor

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CXD1186CQ

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Sony Semiconductor 

5. HOST DMA cycle (SCSI bus)

(1) Read

CXD1186CQ/CR

SDRQ

XSAC

XHRD

HDB0 to 7, P

tDDA

tDAR

tRRL

tDRD

tDRA

tHRD

Item

XSAC fall time (vs. SDRQ ↑)

XSAC delay time (vs. XHRD ↓)

XSAC delay time (vs. XHRD ↑)

Low level XHRD pulse width

Data delay time (vs. XHRD ↓)

Data hold time (vs. XHRD ↑)

Symbol Min.

Typ.

Max.

Unit

tDDA

Tw

n

tDAR

0

n

tDRA

Tw

n

tRRL

T+59

n

tDRD

90

n

tHRD

0

n

(2) Write

SDRQ

XSAC

XHWR

HDB0 to 7, P

tDDA

tDAW

tWWL

tDWA

tSDW

tFWD

Item

XSAC fall time (vs. SDRQ ↑)

XHWR delay time (vs. XSAC ↓)

XSAC delay time (vs. XHWR ↑)

Low level XHWR pulse width

Data setup time (vs. XHWR ↓)

Data float time (vs. XHWR ↓)

Where T in the chart indicates :

Tw for 3 cycle mode

2 • Tw for 4 cycle mode

3 • Tw for 5 cycle mode

Here Tw=1/f

Symbol Min.

Typ.

Max.

Unit

tDDA

Tw

n

tDAW

Tw

n

tDWA

Tw

n

tWWL

T

n

tSDW

T+24

n

tFWD

27

n

—11—

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