LRCK
BCLK
DATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
L0 RV
Rch Validity FLAG
R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 LV
Rch LSB
Rch • MSB
Fig. 2.1.1 (1) Digital In Timing Chart (C2PO don’t care, no need for connection)
LRCK
BCLK
DATA
C2PO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R0
Rch LSB
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Lch MSB
Lch • LSB
C2 Pointer for Upper byte
C2 Pointer for Lower byte
Fig. 2.1.1 (2) CDL30, 35 Series, Timing Chart