CXD1186CQ Просмотр технического описания (PDF) - Sony Semiconductor

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CXD1186CQ

CD-ROM Decoder

Sony Semiconductor 

CXD1186CQ/CR

2. Register function

This IC is controlled from the CPU by means of 19 registers for each of write and read, respectively.

2.1 Write register

2.1.1 Drive Interface (DRVIF) register

bit0 : DIGIN (Digital IN)

“H” ; When Digital In (See fig. 2.1.1) is connected, this bit is set to “H”.

“L” ; When connected to CIRC LSI, this bit is set to “L”.

bits 2 to 5 are effective only when DIGIN is at “L”.

bit1 : LSB1ST (LSB First)

“H” ; When data is connected to CIRC LSI output through LSB first, this bit is set to “H”.

“L” ; When data is connected to CIRC LSI output through MSB first, this bit is set to “L”.

bits2 and 3 : BCKMD 0, 1 (BCLK mode 0, 1)

These bits are set according to the number of BCLK clocks output during one word by CIRC LSI.

BCKMD 1 BCKMD 0

“L”

“L”

16BCLKs/Word

“L”

“H”

24BCLKs/Word

“H”

“X”

32BCLKs/Word

Moreover, when there are 24 or 32 clocks within 1 word, the 16 bits of data before LRCK edge, become

effective.

bit4 : BCKRED (BCLK Rising Edge)

“H” ; Data is strobed with BCLK rise.

“L” ; Data is strobed with BCLK fall.

bit5 : LCHLOW (LCH LOW)

“H” ; When LRCK is at “L”, it is determined to be LCH data.

“L” ; When LRCK is at “H”, it is determined to be LCH data.

∗1. When DIGIN=“H”, We automatically have LSBIST=BCKMD1=“H”, BCKRED=LCHLOW=“L”.

bit6 : DBLSPD (Double Speed)

“H” ; At double speed PB, this bit is set to “H”.

“L” ; At normal speed PB, this bit is set to “L”.

bit7 : C2PLIST (C2PO Lower-byte 1st)

“H” ; When 2 bytes of data are input to C2PO, the Lower-byte and the upper-byte are input in the order.

“L” ; When 2 bytes of data are input to C2PO, the Upper-byte and the lower-byte are input in the order.

Table 2.1.1 indicates the setting value of bits 0 to 7 when Sony-made CIRC LSI is connected. Fig. 2.1.1 (1)

to (4) indicates the input timing chart.

Here, the upper byte means the upper 8 bits including MSB from CIRC LSI, Lower byte indicates the lower 8

bits including LSB from CIRC LSI.

Changes in value for the respective bits in this register have to be executed in the decoder disable condition.

—15—

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