LRCK
BCLK
DATA
C2PO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
R1 R0
Rch LSB
L15 L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
Lch MSB
Lch LSB
C2 Pointer for Upper byte
C2 Pointer for Lower byte
Fig. 2.1.1 (3) CXD2500Q, 48 bit Slot Mode Timing Chart
LRCK
BCLK
DATA
C2PO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
L14 L15
Lch MSB
C2 Pointer for Upper byte
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
Rch LSB
Rch MSB
C2 Pointer for Lower byte
Fig. 2.1.1 (4) CXD2500Q, 64 bit Slot Mode Timing Chart