MAX3420E Просмотр технического описания (PDF) - Maxim Integrated

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MAX3420E

USB Peripheral Controller with SPI Interface

Maxim Integrated 

MAX3420E

USB Peripheral Controller with SPI Interface

Test Circuits and Timing Diagrams

tRISE

tFALL

VOH

90%

10%

VOL

Figure 6. Rise and Fall Times

MAX3420E

33Ω

D+ OR D-

TEST

POINT

CL

15kΩ

Figure 7. Load for D+/D- AC Measurements

tL

SS

tCSS

SCLK

MOSI

HIGH

MISO IMPEDANCE

1

2

tDS

tDH

tCL

tCH

8

9

10

tCP

tDO

tCSW

tT

16

HIGH

IMPEDANCE

Figure 8. SPI Bus Timing Diagram (Full-Duplex Mode, SPI Mode (0,0))

tL

SS

tCSW

tCL

tCH

tT

SCLK

MOSI

1

2

tDS

8

9

10

tCP

16

HI-Z

tDH

tON

tDI

tOFF

MISO HIGH IMPEDANCE

HIGH IMPEDANCE

NOTES:

1) DURING THE FIRST 8 CLOCKS CYCLES, THE MOSI PIN IS HIGH IMPEDANCE AND THE SPI MASTER DRIVES DATA ONTO THE MOSI PIN. SETUP AND HOLD TIMES ARE THE SAME AS

FOR FULL-DUPLEX MODE.

2) FOR SPI WRITE CYCLES, THE MOSI PIN CONTINUES TO BE HIGH IMPEDANCE AND THE EXTERNAL MASTER CONTINUES TO DRIVE MOSI.

3) FOR SPI READ CYCLES, AFTER THE 8TH CLOCK-RISING EDGE, THE MAX3420E STARTS DRIVING THE MOSI PIN AFTER TIME tON. THE EXTERNAL MASTER MUST TURN

OFF ITS DRIVER TO THE MOSI PIN BEFORE tON TO AVOID CONTENTION. PROPAGATION DELAYS ARE THE SAME AS FOR THE MOSI PIN IN FULL-DUPLEX MODE.

Figure 9. SPI Bus Timing Diagram (Half-Duplex Mode, SPI Mode (0,0))

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