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MAX3420E

USB Peripheral Controller with SPI Interface

Maxim Integrated 

MAX3420E

USB Peripheral Controller with SPI Interface

Typical Operating Characteristics

(VCC = +3.3V, VL = +3.3V, TA = +25°C.)

EYE DIAGRAM

4

3

2

1

0

-1

0 10 20 30 40 50 60 70 80

TIME (ns)

Detailed Description

This device contains the digital logic and analog circuitry

necessary to implement a full-speed USB peripheral that

complies with the USB specification rev 2.0. ESD protec-

tion of ±15kV is provided on D+, D-, and VBCOMP. The

MAX3420E features an internal USB transceiver and an

internal 1.5kΩ resistor that connects between D+ and

VCC under the control of a register bit (CONNECT). This

allows a USB peripheral to control the logical connection

to the USB host. Any SPI master can communicate with

the device through the SPI slave interface that operates

in SPI mode (0,0) or (1,1). An SPI master accesses the

MAX3420E by reading and writing to internal registers.

A typical data transfer consists of writing a first byte that

sets a register address and direction with additional bytes

reading or writing data to the register or internal FIFO.

The MAX3420E contains 384 bytes of endpoint buffer

memory, implementing the following endpoints:

●● EP0: 64-byte bidirectional CONTROL endpoint

●● EP1: 2 x 64-byte double-buffered BULK/INT

OUT endpoint

●● EP2: 2 x 64-byte double-buffered BULK/INT IN

endpoint

●● EP3: 64-byte BULK/INT IN endpoint

The choice to use EP1, EP2, EP3 as BULK or INTERRUPT

endpoints is strictly a function of the endpoint descriptors

that the SPI master returns to the USB host during enu-

meration.

The MAX3420E register set and SPI interface is optimized

to reduce SPI traffic. An interrupt output pin, INT, notifies

the SPI master when USB service is required: when a

packet arrives, a packet is sent, or the host suspends

or resumes bus activity. Double-buffered endpoints help

sustain bandwidth by allowing data to move concurrently

over USB and the SPI interface.

VCC

Power the USB transceiver by applying a positive 3.3V

supply to VCC. Bypass VCC to GND with a 1.0µF ceramic

capacitor as close to the VCC pin as possible.

VL

The MAX3420E digital core is powered though the VL pin.

VL also acts as a reference level for the SPI interface and

all other inputs and outputs. Connect VL to the system’s

logic-level power supply. Internal level translators and VL

allow the SPI interface and all general-purpose inputs and

outputs to operate at a system voltage between 1.71V

and 3.6V.

VBCOMP

The MAX3420E features a USB VBUS detector input,

VBCOMP. The VBCOMP pin can withstand input voltag-

es up to 6V. Bypass VBCOMP to GND with a 1.0µF

ceramic capacitor. According to USB specification rev

2.0, a self-powered USB device must not power the

1.5kΩ pullup resistor on D+ if the USB host turns off

VBUS. VBCOMP is internally connected to a voltage

comparator so that the SPI master can detect the loss

of VBUS (through an interrupt (INT) or checking a bit

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