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MAX3420E

USB Peripheral Controller with SPI Interface

Maxim Integrated 

MAX3420E

USB Peripheral Controller with SPI Interface

SPI Half- and Full-Duplex Operation

The MAX3420E can be programmed to operate in

half-duplex (a bidirectional data pin) or full-duplex (one

data-in and one data-out pin) mode. The SPI master sets

a register bit called FDUPSPI (full-duplex SPI) to 1 for

full-duplex, and 0 for half-duplex operation. Half-duplex is

the power-on default.

Full-Duplex Operation

When the SPI master sets FDUPSPI = 1, the SPI inter-

face uses separate data pins, MOSI and MISO to transfer

data. Because of the separate data pins, bits can be

simultaneously clocked into and out of the MAX3420E.

The MAX3420E makes use of this feature by clocking out

8 USB status bits as the command byte is clocked in, as

illustrated in Figure 15.

Reading from the SPI Slave Interface (MISO)

in Full-Duplex Mode

In full-duplex mode the SPI master reads data from the

MAX3420E slave interface using the following steps:

(1) When SS is high, the MAX3420E is unselected and

three-states the MISO output.

(2) After driving SCLK to its inactive state, the SPI mas-

ter selects the MAX3420E by driving SS low. The

MAX3420E turns on its MISO output buffer and places

the first data bit (Q7) on the MISO output (Figure 14).

(3) The SPI master simultaneously clocks the command

byte into the MAX3420E MOSI pin, and USB status

bits out of the MAX3420E MISO pin on the rising

edges of the SCLK it supplies. The MAX3420E changes

its MISO output data on the falling-edges of SCLK.

(4) After eight clock cycles, the master can drive SS high

to deselect the MAX3420E, causing it to three-state

its MISO output. The falling edge of the clock puts

the MSB of the next data byte in the sequence on the

MISO output (Figure 14).

(5) By keeping SS low, the master clocks register data

bytes out of the MAX3420E by continuing to supply

SCLK pulses (burst mode). The master terminates the

transfer by driving SS high. The master must ensure

that SCLK is in its inactive state at the beginning of

the next access (when it drives SS low). In full-duplex

mode, the MAX3420E ignores data on MOSI while

clocking data out on MISO.

Writing to the SPI Slave Interface (MOSI)

in Full-Duplex Mode

In full-duplex mode, the SPI master writes data to the

MAX3420E slave interface through the following steps:

(1) The SPI master sets the clock to its inactive state.

While SS is high, the master can drive the MOSI pin.

(2) The SPI master selects the MAX3420E by driving

SS low and placing the first data bit to write on the

MOSI input.

(3) The SPI master simultaneously clocks the command

byte into the MAX3420E and USB status bits out of the

MAX3420E MISO pin on the rising edges of the SCLK

it supplies. The SPI master changes its MOSI input

data on the falling edges of SCLK.

(4) After eight clock cycles, the master can drive SS high

to deselect the MAX3420E.

(5) By keeping SS low, the master clocks data bytes into

the MAX3420E by continuing to supply SCLK pulses

(burst mode). The master terminates the transfer by

driving SS high. The master must ensure that SCLK

is inactive at the beginning of the next access (when

it drives SS low). In full-duplex mode, the MAX3420E

outputs USB status bits on MISO during the first 8 bits

(the command byte), and subsequently outputs zeroes

on MISO as the SPI master clocks bytes into MOSI.

Half-Duplex Operation

The MAX3420E is put into half-duplex mode at power-

on, or when the SPI master clears the FDUPSPI bit. In

half-duplex mode, the MAX3420E three-states its MISO

pin and makes the MOSI pin bidirectional, saving a pin in

the SPI interface. The MISO pin can be left unconnected in

half-duplex operation.

Because of the single data pin, the USB status bits

available in full-duplex mode are not available as the

SPI master clocks in the command byte. In half-duplex

mode these status bits are accessed in the normal way,

as register bits.

The SPI master must operate the MOSI pin as bidirectional.

It accesses a MAX3420E register as follows:

(1) The SPI master sets the clock to its inactive state.

While SS is high, the master can drive the MOSI pin to

any value.

(2) The SPI master selects the MAX3420E by driving

SS low and placing the first data bit (MSB) to write

on the MOSI input.

(3) The SPI master turns on its output driver and clocks

the command byte into the MAX3420E on the rising

edges of the SCLK it supplies. The SPI master changes

its MOSI data on the falling edges of SCLK.

(4) After eight clock cycles, the master can drive SS

high to deselect the MAX3420E.

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