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MAX3420E

USB Peripheral Controller with SPI Interface

Maxim Integrated 

MAX3420E

USB Peripheral Controller with SPI Interface

GPIN3–GPIN0, GPOUT3–GPOUT0 and GPX

The MAX3420E has four general-purpose inputs

(GPIN3–GPIN0), four general-purpose outputs (GPOUT3–

POUT0), and a multiplexed output pin (GPX). GPIN3

through GPIN0 all have weak internal pullup resistors to

VL. These inputs can be read by sampling bits 7 through

4 of the IOPINS (R20) register. Writing to GPIN3 through

GPIN0 has no effect. GPOUT3 through GPOUT0 are

the general-purpose outputs. Update these outputs by

writing to bits 3 through 0 of the IOPINS (R20) register.

GPOUT3–GPOUT0 logic levels are referenced to the

voltage on VL. As shown in Figure 11, reading the state

of a GPOUT3–GPOUT0 bit returns the state of the inter-

nal register bit, not the actual pin state. This is useful for

doing read-modify-write operations to an output pin (such

as blinking an LED), since the load on the output pin does

not affect the register logic state.

GPX is a push-pull output with a 4-way multiplexer that

selects its output signal. The logic level on GPX is ref-

erenced to VL. The SPI master writes to the GPXB and

GPXA bits of PINCTL (R17) register to select one of four

internal signals as depicted in Table 3.

●● OPERATE: This signal goes high when the

MAX3420E is able to operate after a power-up or

RES reset. OPERATE is the default GPX output.

●● VBUS_DET: VBUS_DET is the VBCOMP comparator

output. This allows the user to directly monitor the

VBUS status.

●● BUSACT: USB BUS activity signal (active-high).

This signal is active whenever there is traffic on

the USB bus. The BUSACT signal is set whenever

a SYNC field is detected. BUSACT goes low during

bus reset or after 32-bit times of J-state.

●● SOF: A square wave with a positive edge that

indicates the USB start-of-frame (Figure 12).

Table 3. GPX Output State

GPXB

0

0

1

1

GPXA

0

1

0

1

GPX PIN OUTPUT

OPERATE (Default State)

VBUS_DET

BUSACT

SOF

GPOUT

WRITE

REGISTER BIT

GPOUT

PIN

GPOUT

READ

Figure 11. Behavior of Read and Write Operations on

GPOUT3–GPOUT0

FULL-SPEED

TIME FRAME

1ms

USB

PACKETS

SOF

GPX

~50%

FULL-SPEED

TIME FRAME

1ms

SOF

SOF

Figure 12. GPX Output in SOF Mode

FDUPSPI = 1

MOSI

MISO

MAX3420E

FDUPSPI = 0

(DEFAULT)

MOSI

MISO

MAX3420E

Figure 13. MAX3420E SPI Data Pins for Full-Duplex (Top) and

Half-Duplex (Bottom) Operation

MOSI (Master-Out, Slave-In) and

MISO (Master-In, Slave-Out)

The SPI data pins MOSI and MISO operate differently

depending on the setting of a register bit called FDUPSPI

(full-duplex SPI). Figure 13 shows the two configurations

according to the FDUPSPI bit setting.

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